User Guide

128-Bit Media and Scientific Programming 185
24592—Rev. 3.15—November 2009 AMD64 Technology
Table 4-14. Masked Responses to SIMD Floating-Point Exceptions
Exception
Operation
1
Processor Response
2
Invalid-
operation
exception (IE)
Any of the following, in which one or both operands is an
SNaN:
Addition (ADDPS, ADDPD, ADDSS, ADDSD,
ADDSUBPD, ADDSUBPS, HADDPS, HADDPD), or
Subtraction (SUBPS, SUBPD, SUBSS, SUBSD,
ADDSUBPD, ADDSUBPS, HSUBPD, HSUBPS), or
Multiplication (MULPS, MULPD, MULSS, MULSD), or
Division (DIVPS, DIVPD, DIVSS, DIVSD), or
Square-root (SQRTPS, SQRTPD, SQRTSS, SQRTSD),
or
Data conversion of floating-point to floating-point
(CVTPS2PD, CVTPD2PS, CVTSS2SD, CVTSD2SS).
Return a QNaN, based on
the rules in Table 4-5 on
page 130.
Addition of infinities with opposite sign (ADDPS, ADDPD,
ADDSS, ADDSD, ADDSUBPS, ADDSUBPD, HADDPD,
HADDPS), or
Subtraction of infinities with same sign (SUBPS, SUBPD,
SUBSS, SUBSD, ADDSUBPS, ADDSUBPD, HSUBPS,
HSUBPD), or
Multiplication of zero by infinity (MULPS, MULPD,
MULSS, MULSD), or
Division of zero by zero or infinity by infinity (DIVPS,
DIVPD, DIVSS, DIVSD), or
Square-root in which the operand is non-zero negative
(SQRTPS, SQRTPD, SQRTSS, SQRTSD).
Return the floating-point
indefinite value.
Any of the following, in which one or both operands is a
NaN:
Maximum or Minimum (MAXPS, MAXPD, MAXSS,
MAXSD MINPS, MINPD, MINSS, MINSD)
Return second source
operand.
Compare, in which one or
both operands is a NaN
(CMPPS, CMPPD, CMPSS,
CMPSD).
Compare is unordered or not-
equal
Return mask of all 1s.
All other compares Return mask of all 0s.
Note:
1. For complete details about operations, see “SIMD Floating-Point Exception Causes” on page 178.
2. In all cases, the processor sets the associated exception flag in MXCSR. For details about number representation,
see “Floating-Point Number Representation” on page 127 and “Floating-Point Number Encodings” on page 130.
3. This response does not comply with the IEEE 754 standard, but it offers higher performance.