User Guide

184 128-Bit Media and Scientific Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
4.10.4 SIMD Floating-Point Exception Masking
The six floating-point exception flags have corresponding exception-flag masks in the MXCSR
register, as shown in Table 4-13.
Each mask bit, when set to 1, inhibits invocation of the exception handler for that exception and
instead causes a default response. Thus, an unmasked exception is one that invokes its exception
handler when it occurs, whereas a masked exception continues normal execution using the default
response for the exception type. During power-on initialization, all exception-mask bits in the MXCSR
register are set to 1 (masked).
Masked Responses. The occurrence of a masked exception does not invoke its exception handler
when the exception condition occurs. Instead, the processor handles masked exceptions in a default
way, as shown in Table 4-14 on page 185.
Table 4-13. SIMD Floating-Point Exception Masks
Exception Mask
and Mnemonic
MXCSR Bit
Comparable IEEE 754
Exception
Invalid-operation exception mask (IM) 7 Invalid Operation
Denormalized-operand exception mask (DM) 8 none
Zero-divide exception mask (ZM) 9 Division by Zero
Overflow exception mask (OM) 10 Overflow
Underflow exception mask (UM) 11 Underflow
Precision exception mask (PM) 12 Inexact