User Guide

182 128-Bit Media and Scientific Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
4.10.3 SIMD Floating-Point Exception Priority
Figure 4-12 on page 182 shows the priority with which the processor recognizes multiple,
simultaneous SIMD floating-point exceptions and operations involving QNaN operands. Each
exception type is characterized by its timing, as follows:
• Pre-Computation—an exception that is recognized before an instruction begins its operation.
• Post-Computation—an exception that is recognized after an instruction completes its operation.
For masked (but not unmasked) post-computation exceptions, a result may be written to the
destination, depending on the type of exception. Operations involving QNaNs do not necessarily cause
exceptions, but the processor handles them with the priority shown in Table 4-12 relative to the
handling of exceptions.
Figure 4-38 on page 183 shows the prioritized procedure used by the processor to detect and report
SIMD floating-point exceptions. Each of the two types of exceptions—pre-computation and post-
computation—is handled independently and completely in the sequence shown. If there are no
unmasked exceptions, the processor responds to masked exceptions. Because of this two-step process,
up to two exceptions—one pre-computation, one post-computation—can be caused by a single
instruction.
Table 4-12. Priority of SIMD Floating-Point Exceptions
Priority Exception or Operation Timing
1
Invalid-operation exception (IE) when accessing
SNaN operand
Pre-Computation
2
Operation involving a QNaN operand
1
—
3
Any other type of invalid-operation exception (IE)
Pre-Computation
Zero-divide exception (ZE)
Pre-Computation
4
Denormalized operation exception (DE)
Pre-Computation
5
Overflow exception (OE)
Post-Computation
Underflow exception (UE)
Post-Computation
6
Precision (inexact) exception (PE)
Post-Computation
Note:
1. Operations involving QNaN operands do not, in themselves, cause exceptions but they are
handled with this priority relative to the handling of exceptions.