User Guide

128-Bit Media and Scientific Programming 173
24592—Rev. 3.15—November 2009 AMD64 Technology
• MAXSD—Maximum Scalar Double-Precision Floating-Point
• MINPS—Minimum Packed Single-Precision Floating-Point
• MINPD—Minimum Packed Double-Precision Floating-Point
• MINSS—Minimum Scalar Single-Precision Floating-Point
• MINSD—Minimum Scalar Double-Precision Floating-Point
The MAXPS and MINPS i nstructions compare each of four single-precision floating-point values in
the first operand with the corresponding single-precision floating-point value in the second operand
and writes the maximum or minimum, respectively, of the two values in the corresponding doubleword
of the destination. The MAXPD and MINPD instructions perform analogous operations on pairs of
double-precision floating-point values.
The MAXSS and MINSS instructions compare the single-precision floating-point value in the low-
order 32 bits of the first operand with the single-precision floating-point value in the low-order 32 bits
of the second operand and writes the maximum or minimum, respectively, of the two values in the low-
order 32 bits of the destination. The three high-order doublewords of the destination XMM register are
not modified.
The MAXSD and MINSD instructions compare the double-precision floating-point value in the low-
order 64 bits of the first operand with the double-precision floating-point value in the low-order 64 bits
of the second operand and writes the maximum or minimum, respectively, of the two values in the low-
order quadword of the destination. The high-order quadword of the destination XMM register is not
modified.
The MINx and MAXx instructions are useful for clamping (saturating) values, such as color values in
3D geometry and rasterization.
Compare and Write rFLAGS
• COMISS—Compare Ordered Scalar Single-Precision Floating-Point
• COMISD—Compare Ordered Scalar Double-Precision Floating-Point
• UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point
• UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point
The COMISS instruction performs an ordered compare of the single-precision floating-point value in
the low-order 32 bits of the first operand with the single-precision floating-point value in the low-order
32 bits of the second operand and sets the zero flag (ZF), parity flag (PF), and carry flag (CF) bits in
the rFLAGS register to reflect the result of the compare. The OF, AF, and SF bits in rFLAGS are set to
zero.
The COMISD instruction performs an analogous operation on the double-precision floating-point
values in the low-order 64 bits of the source operands. The UCOMISS and UCOMISD instructions
perform an analogous, but unordered, compare operations. Figure 4-37 on page 174 shows a COMISD
compare operation.