User Guide

130 128-Bit Media and Scientific Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
bit determines the processor’s response, as described in “SIMD Floating-Point Exception Masking” on
page 184.
When a floating-point operation or exception produces a QNaN result, its value is determined by the
rules in Table 4-5.
4.4.8 Floating-Point Number Encodings
Supported Encodings. Table 4-6 on page 131 shows the floating-point encodings of supported
numbers and non-numbers. The number categories are ordered from large to small. In this affine
ordering, positive infinity is larger than any positive normalized number, which in turn is larger than
any positive denormalized number, which is larger than positive zero, and so forth. Thus, the ordinary
rules of comparison apply between categories as well as within categories, so that comparison of any
two numbers is well-defined.
The actual exponent field length is 8 or 11 bits, and the fraction field length is 23 or 52 bits, depending
on operand precision. The single-precision and double-precision formats do not include the integer bit
in the significand (the value of the integer bit can be inferred from number encodings). Exponents of
both types are encoded in biased format, with respective biasing constants of 127 and 1023.
Table 4-5. NaN Results
Source Operands
(in either order)
NaN Result
1
QNaN
Any non-NaN floating-point value, or
single-operand instructions
Value of QNaN
SNaN
Any non-NaN floating-point value, or
single-operand instructions
Value of SNaN converted to a QNaN
2
QNaN QNaN
Value of operand 1
QNaN SNaN
SNaN QNaN
Value of operand 1 converted to a QNaN
2
SNaN SNaN
Invalid-Operation Exception (IE) occurs without QNaN
or SNaN source operands
Floating-point indefinite value
3
(a special
form of QNaN)
Note:
1. The NaN result is produced when the floating-point invalid-operation exception is masked.
2. The conversion is done by changing the most-significant fraction bit to 1.
3. See “Indefinite Values” on page 131.