User Guide

128-Bit Media and Scientific Programming 119
24592—Rev. 3.15—November 2009 AMD64 Technology
denormals are zeros (DAZ) bit, the processor does not set the DE bit. (See “Denormalized (Tiny)
Numbers” on page 128.)
Zero-Divide Exception (ZE). Bit 2. The processor sets this bit to 1 when a non-zero number is
divided by zero.
Overflow Exception (OE). Bit 3. The processor sets this bit to 1 when the absolute value of a
rounded result is larger than the largest representable normalized floating-point number for the
destination format. (See “Normalized Numbers” on page 128.)
Underflow Exception (UE). Bit 4. The processor sets this bit to 1 when the absolute value of a
rounded non-zero result is too small to be represented as a normalized floating-point number for the
destination format. (See “Normalized Numbers” on page 128.)
When masked by the UM bit (bit 11), the processor only reports a UE exception if the UE occurs
together with a precision exception (PE). Also, see bit 15, the flush-to-zero (FZ) bit.
Precision Exception (PE). Bit 5. The processor sets this bit to 1 when a floating-point result, after
rounding, differs from the infinitely precise result and thus cannot be represented exactly in the
specified destination format. The PE exception is also called the inexact-result exception.
Denormals Are Zeros (DAZ). Bit 6. Software can set this bit to 1 to e nable the DAZ mode, if the
hardware implementation supports this mode. In the DAZ mode, when the processor encounters
source operands in the denormalized format it converts them to signed zero values, with the sign of the
denormalized source operand, before operating on them, and the processor does not set the
denormalized-operand exception (DE) bit, regardless of whether such exceptions are masked or
unmasked.
Support for the DAZ bit is indicated by the MXCSR Mask field in the FXSAVE memory image, as
described in “FXSAVE and FXRSTOR Instructions” in Volume 2. The DAZ mode does not comply
with the IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754).
Exception Masks (PM, UM, OM, ZM, DM, IM). Bits 12–7. Software can set these bits to mask, or
clear this bits to unmask, the corresponding six types of SIMD floating-point exceptions (PE, UE, OE,
ZE, DE, IE). A bit masks its exception type when set to 1, and unmasks it when cleared to 0.
In general, masking a type of exception causes the processor to handle all subsequent instances of the
exception type in a default way (the UE exception has an unusual behavior). Unmasking the exception
type causes the processor to branch to the SIMD floating-point exception service routine when an
exception occurs. For details about the processor’s responses to masked and unmasked exceptions, see
“SIMD Floating-Point Exception Masking” on page 184.
Floating-Point Rounding Control (RC). Bit 14–13. Software uses these bits to specify the rounding
method for 128-bit media floating-point operations. The choices are:
• 00 = round to nearest (default)
• 01 = round down