User Guide

128-Bit Media and Scientific Programming 117
24592—Rev. 3.15—November 2009 AMD64 Technology
Figure 4-12. 128-Bit Media Registers
Upon power-on reset, all 16 XMM registers are cleared to +0.0. However, initialization by means of
the #INIT external input signal does not change the state of the XMM registers.
4.3.2 MXCSR Register
Figure 4-13 on page 118 shows a detailed view of the 128-bit media-instruction control a nd status
register (MXCSR). All bits in this register are read/write. The fields within the MXCSR apply only to
operations performed by 128-bit media instructions. Software can load the register from memory
513-314.eps
XMM Data Registers
127 0
xmm0
xmm1
xmm2
xmm3
xmm4
xmm5
xmm6
xmm7
xmm8
xmm9
xmm10
xmm11
xmm12
xmm13
xmm14
xmm15
Available in all modes
Available only in 64-bit mode
31 0
MXCSR
128-Bit Media Control and Status Register