User Guide

116 128-Bit Media and Scientific Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
Figure 4-11. Move Mask Operation
4.3 Registers
Operands for most 128-bit media instructions are located in XMM registers or memory. Operation of
the 128-bit media instructions is supported by the MXCSR control and status register. A few 128-bit
media instructions—those that perform data conversion or move operations—can have operands
located in MMX™ registers or general-purpose registers (GPRs).
4.3.1 XMM Registers
Sixteen 128-bit XMM data registers, xmm0–xmm15, support the 128-bit media instructions.
Figure 4-12 on page 117 shows these registers. They can hold operands for both vector and scalar
operations with integer and floating-point data types. The high eight XMM registers, xmm8–xmm15,
are available to software running in 64-bit mode for instructions that use a REX prefix (see “REX
Prefixes” on page 74).
513-157..eps
GPR XMM
127 0
concatenate 16 most-significant bits
0