User Guide

General-Purpose Programming 85
24592—Rev. 3.15—November 2009 AMD64 Technology
3.7.9 Branching in 64-Bit Mode
Near Branches in 64-Bit Mode. The long-mode architecture expands the near-branch mechanisms
to accommodate branches in the full 64-bit virtual-address space. In 64-bit mode, the operand size for
all near branches defaults to 64 bits, so these instructions update the full 64-bit RIP.
Table 3-9 lists the near-branch instructions.
The default 64-bit operand size eliminates the need for a REX prefix with these instructions when
registers RAX–RSP (the first set of eight GPRs) are used as operands. A REX prefix is still required if
R8–R15 (the extended set of eight GPRs) are used as operands, because the prefix is required to
address the extended registers.
The following aspects of near branches are controlled by the effective operand size:
• Truncation of the instruction pointer.
• Size of a stack pop or push, resulting from a CALL or RET.
• Size of a stack-pointer increment or decrement, resulting from a CALL or RET.
• Indirect-branch operand size.
In 64-bit mode, all of the above actions are forced to 64 bits. However, the size of the displacement
field for relative branches is still limited to 32 bits.
The operand size of near branches is fixed at 64 bits without the need for a REX prefix. However, the
address size of near branches is not forced in 64-bit mode. Such addresses are 64 bits by default, but
they can be overridden to 32 bits by a prefix.
Table 3-9. Near Branches in 64-Bit Mode
Mnemonic Opcode (hex) Description
Operand Size (bits)
Default
Possible
Overrides
1
CALL E8, FF /2 Call Procedure Near
64 16
Jcc
70 to 7F,
0F 80 to 0F 8F
Jump Conditional
JCXZ
JECXZ
JRCXZ
E3 Jump on CX/ECX/RCX Zero
JMP EB, E9, FF /4 Jump Near
LOOP E2 Loop
LOOPcc E0, E1 Loop if Zero/Equal or Not Zero/Equal
RET C2, C3 Return From Call (near)
Note:
1. There is no 32-bit operand-size override prefix in 64-bit mode.