User Guide

Figures ix
24592—Rev. 3.15—November 2009 AMD64 Technology
Figures
Figure 1-1. Application-Programming Register Set ............................................2
Figure 2-1. Virtual-Memory Segmentation ..................................................10
Figure 2-2. Segment Registers............................................................11
Figure 2-3. Long-Mode Memory Management ...............................................12
Figure 2-4. Legacy-Mode Memory Management .............................................13
Figure 2-5. Byte Ordering ...............................................................14
Figure 2-6. Example of 10-Byte Instruction in Memory ........................................15
Figure 2-7. Complex Address Calculation (Protected Mode) ....................................16
Figure 2-8. Near and Far Pointers .........................................................19
Figure 2-9. Stack Pointer Mechanism ......................................................20
Figure 2-10. Instruction Pointer (rIP) Register ................................................21
Figure 3-1. General-Purpose Programming Registers ..........................................24
Figure 3-2. General Registers in Legacy and Compatibility Modes ...............................25
Figure 3-3. General Registers in 64-Bit Mode ...............................................27
Figure 3-4. GPRs in 64-Bit Mode .........................................................28
Figure 3-5. rFLAGS Register—Flags Visible to Application Software ............................34
Figure 3-6. General-Purpose Data Types ...................................................37
Figure 3-7. Mnemonic Syntax Example ....................................................41
Figure 3-8. BSWAP Doubleword Exchange .................................................48
Figure 3-9. Privilege-Level Relationships ...................................................77
Figure 3-10. Procedure Stack, Near Call .....................................................80
Figure 3-11. Procedure Stack, Far Call to Same Privilege .......................................80
Figure 3-12. Procedure Stack, Far Call to Greater Privilege ......................................81
Figure 3-13. Procedure Stack, Near Return ...................................................82
Figure 3-14. Procedure Stack, Far Return from Same Privilege ...................................83
Figure 3-15. Procedure Stack, Far Return from Less Privilege....................................83
Figure 3-16. Procedure Stack, Interrupt to Same Privilege .......................................89
Figure 3-17. Procedure Stack, Interrupt to Higher Privilege ......................................89
Figure 3-18. I/O Address Space............................................................91
Figure 3-19. Memory Hierarchy Example....................................................97
Figure 4-1. Parallel Operations on Vectors of Integer Elements .................................107