User Guide

68 General-Purpose Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
3.4.2 Canonical Address Format
Bits 63 through the most-significant implemented virtual-address bit must be all zeros or all ones in
any memory reference. See “64-Bit Canonical Addresses” on page 15 for details. (This rule applies to
long mode, which includes both 64-bit mode and compatibility mode.)
3.4.3 Branch-Displacement Size
Branch-address displacements are 8 bits or 32 bits, as in legacy mode, but are sign-extended to 64 bits
prior to using them for address computations. See “Displacements and Immediates” on page 17 for
details.
3.4.4 Operand Size
In 64-bit mode, the following rules apply to operand size:
• 64-Bit Operand Size Option: If an instruction’s operand size (16-bit or 32-bit) in legacy mode
depends on the default-size (D) bit in the current code-segment descriptor and the operand-size
prefix, then the operand-size choices in 64-bit mode are extended from 16-bit and 32-bit to include
64 bits (with a REX prefix), or the operand size is fixed at 64 bits. See “General-Purpose
Instructions in 64-Bit Mode” in Volume 3 for details.
• Default Operand Size: The default operand size for most instructions is 32 bits, and a REX prefix
must be used to change the operand size to 64 bits. However, two groups of instructions default to
64-bit operand size and do not need a REX prefix: (1) near branches and (2) all instructions, except
far branches, that implicitly reference the RSP. See “General-Purpose Instructions in 64-Bit Mode”
in Volume 3 for details.
• Fixed Operand Size: If an instruction’s operand size is fixed in legacy mode, that operand size is
usually fixed at the same size in 64-bit mode. (There are some exceptions.) For example, the
CPUID instruction always operates on 32-bit operands, irrespective of attempts to override the
operand size. See “General-Purpose Instructions in 64-Bit Mode” in Volume 3 for details.
• Immediate Operand Size: The maximum size of immediate operands is 32 bits, as in legacy
mode, except that 64-bit immediates can be MOVed into 64-bit GPRs. When the operand size is 64
bits, immediates are sign-extended to 64 bits prior to using them. See “Immediate Operand Size”
on page 40 for details.
• Shift-Count and Rotate-Count Operand Size: When the operand size is 64 bits, shifts and
rotates use one additional bit (6 bits total) to specify shift-count or rotate-count, allowing 64-bit
shifts and rotates.
3.4.5 High 32 Bits
In 64-bit mode, the following rules apply to extension of results into the high 32 bits when results
smaller than 64 bits are written:
• Zero-Extension of 32-Bit Results: 32-bit results are zero-extended into the high 32 bits of 64-bit
GPR destination registers.