User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
Name Type Polarity/Bus size Description
PER_READY
O High
External Wait Control. Allows external devices connected to the
processor to perform device-paced transfers.
PERBLAST
I Low
Burst Last. This signal is active during non-burst operations and also
during the last transfer of a burst access.
PER_RNW
I Level
Read Not Write. Used to control whether external memory/peripheral
is being read or written.
0 = Write
1 = Read
PPC_IO_IRQ
O 7/High
External Interrupt lines. These lines appear as interrupts 25 to 31
when handled by the physical device's Universal Interrupt Controller
(see
Interrupts).
Configuring the Processor from the Schematic Design
The architecture of the PPC405CR can be configured after placement on the schematic sheet. Simply right-click and choose the
command to configure the processor from the pop-up menu that appears (e.g.
Configure U_PPC405CR (PPC405CR) for a
processor with designator U_PPC405CR). Alternatively, click on the
Configure button, available in the Component Properties
dialog for the processor.
The
Configure (32-bit Processors) dialog will appear as shown in Figure 2.
Figure 2. Options to configure the architecture of the PPC405CR.
The drop-down field at the top-right of the dialog enables you to choose the type of processor you want to work with. As the
pinouts for the Wishbone interfaces between the 32-bit processors are the same, you can easily change the processor used in
your design without having to extensively rewire the external interfaces.
As you select the processor type, the
Configure (32-bit Processors) dialog will change accordingly to reflect the architectural
options available. The symbol on the schematic will also change to reflect the type of processor and configuration options
chosen.
For the PPC405CR, a single architectural option is available that allows you to define the size of the internal memory for the
processor. This memory, also referred to as ‘Low’ or ‘Boot’ memory is implemented using true dual port FPGA Block RAM and
will contain the boot part of a software application and the interrupt and exception handlers.
Speed-critical (or latency-sensitive) parts of an application should also be placed in this memory space.
The following memory sizes are available to choose from:
8 CR0161 (v2.0) March 11, 2008