User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
Architectural Overview
Symbol
Figure 1. PPC405CR symbol.
As can be seen from Figure 1 (previous), the PPC405CR wrapper that is placed in an FPGA design essentially has three
interfaces. The Wishbone External Memory and Peripheral I/O interfaces are identical to those of all other 32-bit processors
supported by Altium Designer.
The third interface provides for connection to the physical PPC405CR itself. More specifically, it caters for:
• Data bus, Address bus and control signals to/from the PPC405CR's External Bus Controller (EBC)
• Clock, Reset and Interrupt signals.
The corresponding signals from the physical PPC405CR must be hardwired to the desired pins of the physical FPGA device. To
wire from the PPC405CR Wishbone wrapper to the physical pins of the FPGA device requires the use of the relevant port-plugin
component (
PROCESSOR_PPC405CR). For more information, refer to the section Placing a PPC405CR in an FPGA design.
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