User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
Improving and Extending Product Life-Cycles
Fast time to market is usually synonymous with a weaker feature set – a traditional trade-off. With FPGA-based system designs
you can have the best of both worlds. You can get your product to market quickly with a limited feature set, then follow-up with
more extensive features over time, upgrading the product while it is already in the field.
This not only extends product life-cycles but also lowers the risk of entry, allowing new protocols to be added dynamically and
hardware bugs to be fixed without product RMA.
Creating Application-Specific Coprocessors
Algorithms can easily be moved between hardware and software implementations. This allows the design to be initially
implemented in software, later off-loading intensive tasks into dedicated hardware, in order to meet performance objectives.
Again, this can happen even after commitment to the board-level design.
Implementing Multiple Processors within a Single Device
Extra processors can be added within a single FPGA device, simply by modifying the design with which the device is
programmed. Once again, this can be achieved after the board-level design has been finalized and a commitment to production
made.
Lowering System Cost
Processors, peripherals, memory and I/O interfaces can be integrated into a single FPGA device, greatly reducing system
complexity and cost. Once the FPGA-based embedded application moves to 32-bit, cost becomes an even more powerful driver.
As large FPGAs become cheaper, both Hybrids and soft cores move into the same general cost area as dedicated processors.
At the heart of this argument is also the idea that once you have paid for the FPGA, any extra IP that you place in the device is
free functionality.
Avoiding Processor Obsolescence
As products mature, processor supply may become an increasing problem, particularly where the processor is one of many
variants supplied by the semiconductor vendor. Switching to a new processor usually requires design software changes or
logical hardware changes.
With FPGA implementations, the design can be easily moved to a different device with little or no change to the hardware logic
and probably no change to the application software. Peripherals are created dynamically in the hardware, so lack of availability
of specific processor variants is never a problem.
The PPC405CR
Altium Designer's support for the AMCC PPC405CR offers you the best of both worlds – allowing you to create designs that
themselves reside within an FPGA device, whilst incorporating the processing power of the PowerPC 405 on the physical
PPC405CR device. Your design may simply provide an extension of the PPC405CR to external memory and peripheral devices,
the interfacing to which is specified in the design downloaded to the FPGA. Alternatively, you may have a hybrid design, making
use not only of a physical processor, but also one or more 'soft' processors defined within your FPGA design and resident on
the target FPGA device. Performance critical code might typically be handled by the physical processor.
The PPC405CR is a 32-bit RISC machine that follows the classic RISC architecture previously described. It is a load/store
machine with 32 general purpose registers.
All instructions are 32-bits wide and most execute in a single clock cycle.
The PPC405CR also features a user-definable amount of zero-wait state block RAM, with true dual-port access.
Wishbone Bus Interfaces
The PPC405CR uses the Wishbone bus standard. This standard is formally described as a
“System-on-Chip Interconnection Architecture for Portable IP Cores”. The current standard is the
Revision B.3 Specification, a copy of which is included as part of the software installation and can
be found by navigating to the Documentation Library » Designing with FPGAs section
of the Knowledge Center panel.
Remember that the PPC405CR
is the 'Wishbone wrapper' placed
in your FPGA design. The actual
embedded PowerPC processor
resides in the physical
PPC405CR device – external to
the FPGA device to which that
design is targeted.
The Wishbone standard is not copyrighted and resides in the public domain. It may be freely
copied and distributed by any means. Furthermore, it may be used for the design and production
of integrated circuit components without royalties or other financial obligations.
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