User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
Figure 10. Detected physical devices appearing in the Hard Devices JTAG chain.
As the physical PPC405CR processor does not reside within an FPGA, communications between the host computer and the
PPC405CR are carried out through the Hard Devices JTAG chain. This is a departure from the normal way of communicating
with FPGA-based, debug-enabled devices, such as the 'soft' processors and virtual instruments, whereby communication is
carried out through the Soft Devices JTAG chain, and in accordance with the Nexus 5001 standard.
For further information on the JTAG communications, refer to the
PC to NanoBoard Communications article.
Additional 'Soft' Devices in Your Design
If your design incorporates FPGA-based 'soft' processors and virtual instruments, in addition to the discrete PPC405CR
processor, these devices will appear in the Soft Devices chain of the
Devices view. The Soft Devices chain is determined when
the design has been implemented within the target FPGA device. It is not a physical chain, in the sense that you can see no
external wiring – the connections required between the Nexus-enabled devices are made internal to the FPGA itself. Figure 11
shows an example of devices presented in this chain.
Figure 11. Nexus-enabled processor (TSK3000A) and virtual instruments appearing in the Soft Devices chain.
Enabling the Soft Devices JTAG Chain
In order to communicate with soft devices in a design (processors and/or virtual instruments) you must enable the Soft Devices
JTAG chain within the design. This is done by placing a JTAG Port (NEXUS_JTAG_CONNECTOR) and corresponding Soft Nexus-
Chain Connector (
NEXUS_JTAG_PORT) on the top schematic sheet of the design, as shown in Figure 12.
If your design incorporates just
the discrete PPC405CR, with no
additional 'soft' devices, then
these Nexus JTAG devices are
not required.
Figure 12. Implementing the soft devices chain within the design.
These devices can be found in the FPGA NB2DSK01 Port-Plugin (FPGA NB2DSK01 Port-Plugin.IntLib) and FPGA
Generic (
FPGA Generic.IntLib) integrated libraries respectively, both of which are located in the \Library\Fpga folder of
the installation.
20 CR0161 (v2.0) March 11, 2008