User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
Placing a PPC405CR in an FPGA Design
Figure 9 shows an example of how a PPC405CR is used within an FPGA design, making peripheral devices and memory (not
shown) available to the physical processor.
Figure 9. Wiring up the PPC405CR wrapper in an FPGA design.
Memory and peripheral I/O devices are wired to the wrapper's Wishbone External Memory and Peripheral I/O interfaces in the
same way as for any other 32-bit processor.
The signals in the wrapper's external interface – the interface to the physical processor itself – must be wired to ports that are
mapped accordingly to the required pins of the physical FPGA device in which the FPGA design will be programmed. You must
ensure that the relevant signals from the discrete processor device are wired to these FPGA device pins.
Facilitating Communications
The host computer is connected to the PPC405CR using the IEEE 1149.1 (JTAG) standard interface. You must ensure that the
physical JTAG lines are appropriately routed between the physical devices on your board.
Verification that the JTAG signals are indeed propagating through the intended physical devices as required is obtained by the
respective physical devices appearing on the Hard Devices chain within the
Devices view (View » Devices View). Figure 10
illustrates this for a board containing an AMCC PPC405CR and a Xilinx Spartan 3 FPGA (XC321000-4FG456C).
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