User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
8-bit peripheral devices should be accessed using the 8-bit LBU and SB instructions. For C-code, this means declaring the
interface to the device as 8 bits wide, for example:
#define Port8 (*(volatile unsigned char*) Port8_Address)
This will result in the software using LBU and SB instructions to access the device.
There are some trade-offs that may need to be considered when deciding whether to use 8-, 16- or 32-bit wide devices. It may
require significantly less hardware to implement a single 32-bit wide I/O port than it would to implement four separate 8-bit ports.
If however, the natural format of the data packets is 8-bits and hardware size is not a constraint, then it may be better to use 8-
bit ports since there will be no need to use software to break up a 32-bit value into smaller components.
If you are only accessing 8-bits at any one time, then software may also execute faster when using 8-bit wide peripherals, since
there is need for extra instructions to extract the 8-bit values from the 32-bit values.
Hardware Description
For detailed information about the hardware and functionality of the PPC405CR processor, including internal registers, refer to
the following document, available from the
AMCC website:
•
PPC405CR Embedded Processor User's Manual
Clocking
The signal PPC_SYS_CLK sent from the processor wrapper to the physical processor itself is simply the internally-routed CLK_I
signal. On the physical device side, the PPC_SYS_CLK signal (arriving as SysClk) is fed into a PLL. The generated PER_CLK
signal is then sent back into the FPGA, where it is used to correctly clock signals to/from the wrapper.
PPC_SYS_CLK – and therefore CLK_I – must be within the range 25MHz to 66MHz, in order for the PLL to achieve stable
locking.
Reset
The signal PPC_SYS_RESET sent from the processor wrapper to the physical processor itself (arriving as SysReset) is simply
the internally-routed RST_I signal. A system reset of the FPGA can therefore also be used to reset the physical processor as
well.
Conversely, the physical processor can issue a reset of the system, the required signal of which (ExtReset) is passed into the
FPGA, ultimately arriving at the wrapper on the PER_RESET line.
Interrupts
Although the PPC405CR wrapper has provision for 32 interrupt lines, the physical PowerPC device supports only 7 external
interrupts. The least significant 7 lines of the INT_I bus are connected through to the PPC_IO_IRQ bus.
These external interrupts are handled by a Universal Interrupt Controller (UIC) – part of the physical PPC405CR device, but
external to the embedded PowerPC 405 processor itself. They appear as interrupts 25 to 31. The interrupt handler combines
these signals into a single signal sent to the processors Noncritical interrupt input.
Interrupts generated by Altium Designer Wishbone peripherals have positive polarity and are level sensitive. You will need to
program the processor's UIC Polarity Register (UIC0_PR) with '1's (positive polarity) for the corresponding external interrupt
bits. You will also need to ensure that the corresponding bits in the UIC Trigger Register (UIC0_TR) are set to '0' (level
sensitive). Bear in mind that the internal registers use reverse-bit logic, so the external interrupts (bits 25-31) are the right-
most 7 bits in the register.
Detailed information on the operation of the PPC405CR's Interrupt Controller can be found in the
Interrupt Controller
Operations
section of the PPC405CR Embedded Processor User's Manual.
16 CR0161 (v2.0) March 11, 2008