User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
0xFFFF_FFE4 mtdcr PeripheralControl_Data,%R4
; Memory controller now configured. Now jump out to address 0000_0000h,
; fetch whatever is in block RAM and proceed with user application.
0xFFFF_FFE8 ba 0x00000000
; the following nops are for alignment only. They are required as the last
; instruction (b _START) has to be placed at the processor's reset vector
; address.
0xFFFF_FFEC nop
0xFFFF_FFF0 nop
0xFFFF_FFF4 nop
0xFFFF_FFF8 nop
; The processor will fetch the following instruction first after a reset and
; will branch to _START label so we can configure memory controller prior to
; giving control to the user code at address 0000_0000h in block RAM.
0xFFFF_FFFC b _START ; jbranch to 0xFFFF_FFC0
Peripheral I/O Interface Time-out
A simple time-out mechanism for the interface handles the case when attempting to access an address that does not exist, or if
the addressed target slave device is not operating correctly. This mechanism ensures that the processor will not be ‘locked’
indefinitely, waiting for an acknowledgement on its IO_ACK_I input.
After the IO_STB_O output is taken High a timer built-in to Altium Designer's PPC405CR wrapper is started and the physical
PPC405CR processor, which normally times out after 16 cycles, is requested to wait. If, after 4096 cycles of the external clock
signal (CLK_I), an acknowledge signal fails to appear from the addressed slave peripheral device, the wait request to the
PPC405CR is dropped, the processor times out normally and the current data transfer cycle is forcibly terminated.
The ACK_O signal from a slave peripheral should not be used as a ‘long delay’ hand-shaking mechanism. Where such a
mechanism needs to be implemented, either use polling or interrupts.
For more information on connection of slave physical memory and peripheral I/O devices to the processor's Wishbone
interfaces, refer to the application note
Connecting Memory and Peripheral Devices to a 32-bit Processor.
Data Organization
Data organization refers to the ordering of the data during transfers. There are two general types of ordering:
• BIG ENDIAN – the most significant portion of an operand is stored at the lower address
•
LITTLE ENDIAN – the most significant portion of an operand is stored at the higher address.
The physical PPC405CR supports both of these, but by default operates in Big Endian mode only. Little Endian mode is not
implemented.
Words, Half-Words and Bytes
The PPC405CR operates on the following data sizes:
• 32-bit words
• 16-bit half-words
• 8-bit bytes.
There are dedicated load and store instructions for these three data types.
Figure 7 shows how these different sizes of data are organized relative to each other over an 8-byte memory range in the
PPC405CR.
14 CR0161 (v2.0) March 11, 2008