User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
This memory still has the standard limitation of load delay slots, because the load from memory happens further down the
pipeline, after the Execute stage. As a result, any operation that requires loaded data in the cycle immediately after the load will
cause the processor to insert a load stall, holding the first half of the pipeline for one cycle while the data becomes available.
Other than this single limitation, the RAM block is as fast as the internal processor registers themselves.
The size of the RAM can vary between 1KB and 16MB, dependent on the availability of embedded block RAM in the target
FPGA device used. Memory size is configured in the
Internal Processor Memory region of the Configure (32-bit Processors)
dialog (see the Configuring the Processor from the Schematic Design section).
Covering the processor's address space between 0000_0000h and 00FF_FFFFh, it will contain the reset and interrupt vectors,
as well as any speed or latency-sensitive code or data.
External Memory
The PPC405CR wrapper's Wishbone External Memory Interface is used by both the instruction and data sides of the processor
and provides access to the majority of the address space of the processor. It covers the address space between 0100_0000h
and FF00_0000h – 1.
External Memory Interface Time-out
A simple time-out mechanism for the interface handles the case when attempting to access an address that does not exist, or if
the addressed target slave device is not operating correctly. This mechanism ensures that the processor will not be ‘locked’
indefinitely, waiting for an acknowledgement on its ME_ACK_I input.
After the ME_STB_O output is taken High a timer built-in to Altium Designer's PPC405CR wrapper is started and the physical
PPC405CR processor, which normally times out after 16 cycles, is requested to wait. If, after 4096 cycles of the external clock
signal (CLK_I), an acknowledge signal fails to appear from the addressed slave memory device, the wait request to the
PPC405CR is dropped, the processor times out normally and the current data transfer cycle is forcibly terminated.
The ACK_O signal from a slave device should not be used as a ‘long delay’ hand-shaking mechanism. Where such a
mechanism needs to be implemented, either use polling or interrupts.
Peripheral I/O
The PPC405CR wrapper's Wishbone Peripheral I/O Interface is a one-way Wishbone Master, handling I/O in a very similar way
to external memory. The port can be used to communicate with any Wishbone Slave peripheral device and covers the address
space between FF00_0000h and FFFF_FFFFh. This address space of 16MB allows a physical address bus size of 24 bits.
Although the space for peripheral I/O is 16MB, the top 256 bytes is reserved for hardwired boot code (see next section). Any
access to addresses in the range FFFF_FF00h to FFFF_FFFFh over the Wishbone Peripheral I/O interface will be ignored.
System Boot Code
The region of processor address space from FFFF_FF00h to FFFF_FFFFh is reserved for system boot (or startup) code. After a
reset, the processor will try to fetch its first instruction from address FFFF_FFFCh, as this is the reset vector for the PPC405CR.
In order to make the physical processor compatible with the standard Wishbone memory layout – employed for all 32-bit
processors in Altium Designer – the memory controller in the physical device needs to be configured accordingly. This entails
use of the following hardwired instructions within the Wishbone wrapper around the processor, the result of which is to configure
the physical processor's memory controller, then branch to address 0000_0000h in the boot RAM (block RAM) containing the
user code.
_START:
; EBC Access Parameters
0xFFFF_FFC0 li %R4,EBC0_B1AP
0xFFFF_FFC4 mtdcr PeripheralControl_Address,%R4
0xFFFF_FFC8 lis %R4 ,@MSH(EBC_FastBRAM)
While addresses in the
range FFFF_FF00h to
FFFF_FFFFh are
reserved for the hardwired
boot code, only addresses
from FFFF_FFC0h to
FFFF_FFFFh are actually
used.
0xFFFF_FFCC ori %R4,%R4,@LSH(EBC_FastBRAM)
0xFFFF_FFD0 mtdcr PeripheralControl_Data,%R4
; EMC Configuration Registers
0xFFFF_FFD4 li %R4,EBC0_B1CR
0xFFFF_FFD8 mtdcr PeripheralControl_Address,%R4
0xFFFF_FFDC lis %R4 ,@MSH(EBC_16MB_32Bit_RAM_000)
0xFFFF_FFE0 ori %R4,%R4,@LSH(EBC_16MB_32Bit_RAM_000)
CR0161 (v2.0) March 11, 2008 13