User`s manual

PPC405CR – AMCC PowerPC 32-bit RISC Processor
The adjacent flow chart shows the process that was followed to build this memory map in the FPGA
project. This flow chart is only a guide, during the course of development it is likely that you will
jump back and forth through this process as you build up the design.
Place Processor
Place Wishbone
Interconnect
Configure Processor
to see Peripherals
(import settings from WB
intercon)
Peripheral memory
map ready for
embedded project
(repeat process for
memory)
(peripheral n)
(peripheral 2)
Place peripheral
component on
schematic
(peripheral 1)
(Add and Setup Pn)
(Add and Setup P2)
Configure
Wishbone
Interconnect
(Add and Setup P1)
The flow of connecting and
mapping the peripherals (or
memory) to the processor
Dedicated System Interconnect Components
This process of being able to quickly build up the design and resolve the processor to memory &
peripheral interface is possible because of specialized interconnection components, including the
Wishbone Interconnect, the Wishbone Dual Master and the Wishbone Multi-Master.
These three components solve the common system interconnect issues that face the designer,
these being:
• Interfacing multiple peripheral and memory blocks to a processor (handled by the Wishbone
Interconnect component)
• Allowing two or more system components, that must each be able to control the bus, to share
access to a common resource (provided by the Wishbone Dual Master or Wishbone Multi-
Master components)
Use of the Wishbone Interconnection Architecture for all parts of the system that connect to the
processor contributes to the system’s ‘building block’ behavior. The Wishbone standard resolves
data exchange between system components – supporting popular data transfer bus protocols, while
defining clocking, handshaking and decoding requirements (amongst others).
With the lower-level physical interface requirements being resolved by the Wishbone interface, the
other challenge is the structural aspects of the system – defining where components sit in the
address space, providing address decoding, and allocating and interfacing interrupts to the
processor.
For more information on the Wishbone Interconnect component, refer to the
WB_INTERCON
Configurable Wishbone Interconnect
core reference.
For more information on the Wishbone Dual Master component, refer to the
WB_DUALMASTER
Configurable Wishbone Dual Master
core reference.
For more information on the Wishbone Multi-Master component, refer to the
WB_MULTIMASTER Configurable Wishbone Multi-Master core reference.
Configuring the Processor
Each configurable component has its own configuration dialog, including the different processors.
The processor has separate commands and dialogs to configure memory and peripherals, but it
does support mapping peripherals into memory space (and the memory into peripheral space), if
required.
An important feature to point out is the
Import from Schematic button in the processor’s Configure
dialogs, clicking this will read in the settings from the Interconnects attached to the processor. This
lets you quickly build the memory map, as shown in the figure earlier. You now have the memory
map defined in the hardware, this data is stored with the processor component.
The processor’s
Configure dialogs include options to generate assembler and C hardware description files that can be included
in your embedded project, simplifying the task of declaring peripheral and memory structures in your embedded code. You can
also ‘pull’ the memory map configurations directly into the embedded project by enabling the Automatically import when
compiling FPGA project
option in the Configure Memory tab of the Options for Embedded Project dialog.
For more information on mapping physical memory devices and I/O peripherals into the processor's address space, refer to
the application note
Allocating Address Space in a 32-bit Processor.
Division of Memory Space
As illustrated previously (Figure 4), the PPC405CR's 4GB address space is divided into three distinct areas (or ranges). Memory
and peripheral devices defined within the FPGA design are mapped into these regions, as detailed in the following sections.
Internal Memory
The internal "Low" or "Boot" RAM is built using true dual-port FPGA block RAM memory. As such, it can be read or written on
both sides, simultaneously, in a single cycle.
12 CR0161 (v2.0) March 11, 2008