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PPC405CR – AMCC

PowerPC

32-bit RISC

Processor

Summary

Core Reference

CR0161 (v2.0) March 11, 2008

This document provides information on Altium Designer's Wishbone wrapper support

for the discrete AMCC

PPC405CR – an embedded PowerPC

405 32-bit RISC

processor.

Altium Designer's PPC405CR component is a 32-bit Wishbone-compatible RISC processor.

Although placed in an Altium Designer-based FPGA project just like any other 32-bit processor component, the PPC405CR is

essentially a Wishbone-compliant wrapper that allows communication with, and use of, the discrete PowerPC 405 processor

encapsulated within the AMCC PPC405CR device. You can think of the wrapper as being the 'means' by which to facilitate use

of external memory and peripheral devices – defined within an FPGA – with the discrete processor.

Most instructions are 32-bits wide and execute in a single clock cycle. In addition to fast register access, the PPC405CR

features a user-definable amount of zero-wait state block RAM, with true dual-port access

The PPC405CR wrapper can be used in FPGA designs targeting any physical FPGA device – you are not constrained to a

particular vendor or platform.

Features

• 5-stage pipelined RISC processor

• Internal Harvard architecture with simplified external memory access

• 4GByte address space

• Wishbone I/O and memory ports for simplified peripheral connection

• Full Viper-based software development tool chain – C compiler/assembler/source-level debugger/profiler

• C-code compatible with other Altium Designer 8-bit and 32-bit Wishbone-compliant processors, for easy design migration.

For further information on PPC405CR features, refer to the following documents, available from

www.amcc.com/Embedded:

•

PPC405CR Data Sheet (DS2007)

•

PPC405CR Embedded Processor User's Manual.

Available Devices

The PPC405CR device can be found in the FPGA Processors integrated library (FPGA Processors.IntLib), located in the

\Library\Fpga folder of the installation.

CR0161 (v2.0) March 11, 2008 1

Summary of content (25 pages)

PAGE 1
® ® PPC405CR – AMCC PowerPC 32-bit RISC Processor Summary Core Reference This document provides information on Altium Designer's Wishbone wrapper support ® ® for the discrete AMCC PPC405CR – an embedded PowerPC 405 32-bit RISC processor. CR0161 (v2.0) March 11, 2008 Altium Designer's PPC405CR component is a 32-bit Wishbone-compatible RISC processor.
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PPC405CR – AMCC PowerPC 32-bit RISC Processor RISC Processor Background RISC, or Reduced Instruction Set Computer, is a term that is conventionally used to describe a type of microprocessor architecture that employs a small but highly-optimized set of instructions, rather than the large set of more specialized instructions often found in other types of architectures. This other type of processor is traditionally referred to as CISC, or Complex Instruction Set Computer.
PAGE 3
PPC405CR – AMCC PowerPC 32-bit RISC Processor Improving and Extending Product Life-Cycles Fast time to market is usually synonymous with a weaker feature set – a traditional trade-off. With FPGA-based system designs you can have the best of both worlds. You can get your product to market quickly with a limited feature set, then follow-up with more extensive features over time, upgrading the product while it is already in the field.
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PPC405CR – AMCC PowerPC 32-bit RISC Processor Wishbone OpenBUS Processor Wrappers To normalize access to hardware and peripherals, each of the 32-bit processors supported in Altium Designer has a Wishbone OpenBUS-based FPGA core that 'wraps' around the processor. This enables peripherals defined in the FPGA to be used transparently with any type of processor. An FPGA OpenBUS wrapper around discrete, hard-wired peripherals also allows them to be moved seamlessly between processors.
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PPC405CR – AMCC PowerPC 32-bit RISC Processor Architectural Overview Symbol Figure 1. PPC405CR symbol. As can be seen from Figure 1 (previous), the PPC405CR wrapper that is placed in an FPGA design essentially has three interfaces. The Wishbone External Memory and Peripheral I/O interfaces are identical to those of all other 32-bit processors supported by Altium Designer. The third interface provides for connection to the physical PPC405CR itself.
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PPC405CR – AMCC PowerPC 32-bit RISC Processor Pin Description Table 1. PPC405CR pin description Name Type Polarity/Bus size Description Control Signals CLK_I I Rise External (system) clock. This signal is internally wired to the PPC_SYS_CLK output. RST_I I High External (system) reset. This signal is internally wired to the PPC_SYS_RESET output. Interrupt Signals INT_I I 32 Interrupt lines.
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PPC405CR – AMCC PowerPC 32-bit RISC Processor Name Type Polarity/Bus size Description IO_ACK_I I High Standard Wishbone device acknowledgement signal.
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PPC405CR – AMCC PowerPC 32-bit RISC Processor Name Type Polarity/Bus size Description PER_READY O High External Wait Control. Allows external devices connected to the processor to perform device-paced transfers. PERBLAST I Low Burst Last. This signal is active during non-burst operations and also during the last transfer of a burst access. PER_RNW I Level Read Not Write. Used to control whether external memory/peripheral is being read or written.
PAGE 9
PPC405CR – AMCC PowerPC 32-bit RISC Processor • 1KB (256 x 32-bit Words) • 2KB (512 x 32-bit Words) • 4KB (1K x 32-bit Words) • 8KB (2K x 32-bit Words) • 16KB (4K x 32-bit Words) • 32KB (8K x 32-bit Words) • 64KB (16K x 32-bit Words) • 128KB (32K x 32-bit Words) • 256KB (64K x 32-bit Words) • 512KB (128K x 32-bit Words) • 1MB (256K x 32-bit Words) Your configuration choice will be reflected in the Current Configuration region of the processor’s schematic symbol (Figure 3).
PAGE 10
PPC405CR – AMCC PowerPC 32-bit RISC Processor Memory & I/O Management The PPC405CR uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. Memory space is broken into three main areas, as illustrated in Figure 4. Memory and peripheral I/O devices placed and wired within the FPGA design are mapped into this space. Further information can be found in the section – Division of Memory Space.
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PPC405CR – AMCC PowerPC 32-bit RISC Processor Figure 5. Memory devices mapped into the PPC405CR's address space. Figure 6. Peripheral devices mapped into the PPC405CR's address space. CR0161 (v2.
PAGE 12
PPC405CR – AMCC PowerPC 32-bit RISC Processor The adjacent flow chart shows the process that was followed to build this memory map in the FPGA project. This flow chart is only a guide, during the course of development it is likely that you will jump back and forth through this process as you build up the design.
PAGE 13
PPC405CR – AMCC PowerPC 32-bit RISC Processor This memory still has the standard limitation of load delay slots, because the load from memory happens further down the pipeline, after the Execute stage. As a result, any operation that requires loaded data in the cycle immediately after the load will cause the processor to insert a load stall, holding the first half of the pipeline for one cycle while the data becomes available.
PAGE 14
PPC405CR – AMCC PowerPC 32-bit RISC Processor 0xFFFF_FFE4 mtdcr PeripheralControl_Data,%R4 ; Memory controller now configured. Now jump out to address 0000_0000h, ; fetch whatever is in block RAM and proceed with user application. 0xFFFF_FFE8 ba 0x00000000 ; the following nops are for alignment only. They are required as the last ; instruction (b _START) has to be placed at the processor's reset vector ; address.
PAGE 15
PPC405CR – AMCC PowerPC 32-bit RISC Processor Word-0 31 24 23 16 Word-1 15 8 Half-0 15 8 7 0 15 Byte-1 0 0 31 24 Half-1 7 Byte-0 7 7 8 0 7 0 15 Byte-3 0 16 15 8 Half-2 7 Byte-2 23 7 8 0 7 0 15 Byte-5 0 7 0 Half-3 7 Byte-4 7 8 7 Byte-6 0 7 0 Byte-7 0 7 0 Figure 7. Organization of data types for the PPC405CR (Big Endian). Physical Interface to Memory and Peripherals The PPC405CR's physical interface to the outside world is always 32 bits wide.
PAGE 16
PPC405CR – AMCC PowerPC 32-bit RISC Processor 8-bit peripheral devices should be accessed using the 8-bit LBU and SB instructions. For C-code, this means declaring the interface to the device as 8 bits wide, for example: #define Port8 (*(volatile unsigned char*) Port8_Address) This will result in the software using LBU and SB instructions to access the device. There are some trade-offs that may need to be considered when deciding whether to use 8-, 16- or 32-bit wide devices.
PAGE 17
PPC405CR – AMCC PowerPC 32-bit RISC Processor Wishbone Communications The following sections detail the standard handshaking that takes place when the processor communicates to a slave peripheral or memory device connected to the relevant Wishbone interface port. Both of the PPC405CR wrapper's Wishbone ports can be configured for 8-, 16- or 32-bit data transfer, depending on the width of the data bus supported by the connected slave device.
PAGE 18
PPC405CR – AMCC PowerPC 32-bit RISC Processor Reading from a Slave Wishbone Memory Device Data is read by the host processor (Wishbone Master) from a Wishbone-compliant memory device or memory controller (Wishbone Slave) in accordance with the standard Wishbone data transfer handshaking protocol. This data transfer cycle can be summarized as follows: • The host presents an address on its ME_ADR_O output for the address in memory that it wishes to read.
PAGE 19
PPC405CR – AMCC PowerPC 32-bit RISC Processor Placing a PPC405CR in an FPGA Design Figure 9 shows an example of how a PPC405CR is used within an FPGA design, making peripheral devices and memory (not shown) available to the physical processor. Figure 9. Wiring up the PPC405CR wrapper in an FPGA design. Memory and peripheral I/O devices are wired to the wrapper's Wishbone External Memory and Peripheral I/O interfaces in the same way as for any other 32-bit processor.
PAGE 20
PPC405CR – AMCC PowerPC 32-bit RISC Processor Figure 10. Detected physical devices appearing in the Hard Devices JTAG chain. As the physical PPC405CR processor does not reside within an FPGA, communications between the host computer and the PPC405CR are carried out through the Hard Devices JTAG chain.
PAGE 21
PPC405CR – AMCC PowerPC 32-bit RISC Processor Downloading Your Design Download of a design which incorporates a discrete processor such as the PPC405CR is performed in two stages: • Download of the FPGA design to the target physical FPGA device. This includes downloading the respective embedded code to any 'soft' processors used within the design.
PAGE 22
PPC405CR – AMCC PowerPC 32-bit RISC Processor On-Chip Debugging To facilitate real-time debugging of the processor, the PPC405CR includes On-Chip Debug hardware that can be accessed using the standard JTAG interface.
PAGE 23
PPC405CR – AMCC PowerPC 32-bit RISC Processor The debug environment offers the full suite of tools you would expect to see in order to efficiently debug the embedded code. These features include: • Setting Breakpoints • Adding Watches • Stepping into and over at both the source (*.C) and instruction (*.asm) level • Reset, Run and Halt code execution • Run to cursor All of these and other feature commands can be accessed from the Debug menu or the associated Debug toolbar.
PAGE 24
PPC405CR – AMCC PowerPC 32-bit RISC Processor Full-feature debugging is of course enjoyed at the source code level – from within the source code file itself. To a lesser extent, debugging can also be carried out from a dedicated debug panel for the processor. To access 1 this panel, first double-click on the icon representing the physical PPC405CR device, in the Hard Devices region of the view. The Instrument Rack – Hard Devices panel will appear, with the PPC405CR device added to the rack (Figure 16).
PAGE 25
PPC405CR – AMCC PowerPC 32-bit RISC Processor For more information on the content and use of processor debug panels, press F1 when the cursor is over one of these panels. For further information regarding the use of the embedded tools for the PPC405CR, see the Using the PowerPC Embedded Tools guide. For comprehensive information with respect to the embedded tools available for the PowerPC, see the PowerPC Embedded Tools Reference.