Specifications

PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.08 – March 24, 2008
AMCC 5
Data Sheet
Figure 1. PPC405EP Embedded Controller Functional Block Diagram
The PPC405EP is designed using the IBM Microelectronics Blue Logic
TM
methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect
TM
Bus Architecture.
PPC405
Processor Core
DOCM
IOCM
DCU
ICU
OCM
Control
OCM
SRAM
DCR Bus
16KB
On-chip Peripheral Bus (OPB)
GPIO
IIC GPT
UART
MAL
Ethernet
DMA
Bridge
Processor Local Bus (PLB)
SDRAM
PCI Bridge
External
Bus
Controller
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
MII
Controller
OPB
Interrupt
Controller
Arb
29-bit addr
16-bit data
13-bit addr
32-bit data
Universal
I-Cache
D-Cache
(4-Channel)
66 MHz max (async)
DCRs
16KB
Arb
x2
x2
Event
Counters