Specifications

PPC405EP – PowerPC 405EP Embedded Processor
48 AMCC
Revision 1.08 – March 24, 2008
Data Sheet
Table 15. I/O Specifications—Group 2
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I
OH
is specified at 2.4V and I
OL
is specified at 0.4V.
Signal
Input (ns) Output (ns) Output Current (mA)
Clock Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I
OH
(minimum)
I
OL
(minimum)
SDRAM Interface
BA1:0 na na 4.7 2 15.3 10.2 MemClkOut 1, 2
BankSel3:0
na na 4.5 1.7 15.3 10.2 MemClkOut 1, 2
CAS
na na 4.8 2 15.3 10.2 MemClkOut 1, 2
ClkEn0:1 na na 4.1 1.6 28.7 19.3 MemClkOut 1, 2
DQM0:3 na na 4.7 1.9 15.3 10.2 MemClkOut 1, 2
MemAddr12:00 na na 4.8 2.1 15.3 10.2 MemClkOut 1, 2
MemData00:31 1.6 1 4 1.2 15.3 10.2 MemClkOut 1, 2
RAS
na na 5 2.1 15.3 10.2 MemClkOut 1, 2
WE
na na 4.9 2 15.3 10.2 MemClkOut 1, 2
External Slave Peripheral Interface
PerAddr06:31 na na 3.8 1.6 15.3 10.2 PerClk
[PerBLast
]4180128PerClk
PerCS0
[PerCS1:4]
na na 4.1 1.5 10.3 7.1 PerClk
PerData00:31 5 1 6.4 1.5 15.3 10.2 PerClk
PerOE
na na 4.1 1.5 10.3 7.1 PerClk
PerR/W
na na 4.1 1.6 10.3 7.1 PerClk
PerReady 6.5 1 na na na na PerClk
PerWBE0:3
na na 4.1 1.6 10.3 7.1 PerClk
ExtReset
na na na na 15.3 10.2 PerClk
PerClk na na 0.4 -0.2 15.3 10.2 PLB Clk 4