Specifications

PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.08 – March 24, 2008
AMCC 47
Data Sheet
Internal Peripheral Interface
IICSCL na na na na 15.3 10.2
IICSDA na na na na 15.3 10.2
UART0_CTS
na na na na na na
UART0_RTS
na na na na 10.3 7.1
UART0_Rx nananananana
UART0_Tx na na na na 10.3 7.1
UART1_Rx nananananana
UART1_Tx na na na na 10.3 7.1
Interrupts Interface
[IRQ0:6] 10.3 7.1
JTAG Interface
TCK nanananananaasync
TDI na na na na na na async
TDO na na na na 10.3 7.1 async
TMS nanananananaasync
TRST
na na na na na na async
System Interface
GPIO00:31 na na na na 10.3 7.1
Halt
na na na na na na async
SysErr na na na na 10.3 7.1 async
SysReset
na na na na 10.3 7.1 async
TestEn na na na na na na async
[RejectPkt0:1] 3 1 na na na na async
SysClk na na na na na na
Table 14. I/O Specifications—Group 1 (Sheet 2 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.
3. For PCI, I
OH
is specified at 0.9OV
DD
and I
OL
is specified at 0.1OV
DD
. For all other interfaces, I
OH
is specified at 2.4V and I
OL
is specified at 0.4V.
Signal
Input (ns) Output (ns) Output Current (mA)
Clock Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I
OH
(min)
I
OL
(min)