Specifications

PPC405EP – PowerPC 405EP Embedded Processor
46 AMCC
Revision 1.08 – March 24, 2008
Data Sheet
Table 14. I/O Specifications—Group 1 (Sheet 1 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.
3. For PCI, I
OH
is specified at 0.9OV
DD
and I
OL
is specified at 0.1OV
DD
. For all other interfaces, I
OH
is specified at 2.4V and I
OL
is specified at 0.4V.
Signal
Input (ns) Output (ns) Output Current (mA)
Clock Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I
OH
(min)
I
OL
(min)
PCI Interface
PCIAD31:00 3 0 6 1 0.5 1.5 PCIClk 1
PCIC3:0/BE3:0
30 6 10.51.5PCIClk1
PCIClk na na na na na na async
PCIDevSel
30 6 10.51.5PCIClk1
PCIFrame
30 6 10.51.5PCIClk1
PCIGnt0
/Req
PCIGnt1:2
na na 6 1 0.5 1.5 PCIClk 1
PCIIDSel 30nanananaPCIClk1
PCIINT
[PerWE] na na na na 0.5 1.5 PCIClk 1
PCIIRDY
30 6 10.51.5PCIClk1
PCIParity 3 0 6 1 0.5 1.5 PCIClk 1
PCIPErr
30 6 10.51.5PCIClk1
PCIReq0
/Gnt
PCIReq1:2
5 0 na na na na PCIClk 1
PCIReset
na na na na 0.5 1.5 PCIClk 1
PCISErr
na na na na 0.5 1.5 PCIClk 1
PCIStop
30 6 10.51.5PCIClk1
PCITRDY
30 6 10.51.5PCIClk1
Ethernet Interface
EMC0MDClk na na settable 2 10.3 7.1 async 2
EMC0MDIO na na na na 10.3 7.1 EMC0MDClk 2
EMC0Tx0:1D3:0 na na 14 5 10.3 7.1 PHY0TxClk 2
EMC0Tx0:1En na na 14 5 10.3 7.1 PHY0TxClk 2
EMC0Tx0:1Err na na 14 5 10.3 7.1 PHY0TxClk 2
PHY0Col0:1 2 3 na na na na PHY0RxClk 2
PHY0CrS0:1 2 3 na na na na PHY0RxClk 2
PHY0Rx0:1Clk na na na na na na async 2
PHY0Rx0:1D3:0 2 4 na na na na PHY0RxClk 2
PHY0Rx0:1DV 24nanananaPHY0RxClk2
PHY0Rx0:1Err 2 4 na na na na PHY0RxClk 2
PHY0Tx0:1Clk na na na na na na async 2