Specifications

PPC405EP – PowerPC 405EP Embedded Processor
40 AMCC
Revision 1.08 – March 24, 2008
Data Sheet
Table 11. DC Electrical Characteristics
Parameter Symbol Minimum Typical Maximum Unit
Active Operating Current (V
DD
)–266MHz I
DD
300 610 mA
Active Operating Current (V
DD
)–333MHz I
DD
325 690 mA
Active Operating Current (OV
DD
)I
ODD
45 200 mA
PLL V
DD
Input current I
PLL
16 23 mA
Active Operating Power–266 MHz
P
DD
0.72 1.92 W
Active Operating Power–333MHz
P
DD
0.76 2.07 W
Note:
1. The maximum current and power values listed above are not guaranteed to be the highest obtainable. These values are
dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external
interface usage, case temperature, and the power supply voltages. Your specific application can produce significantly different
results. V
DD
(logic) current and power are primarily dependent on the applications running and the use of internal chip functions
(DMA, PCI, Ethernet, and so on). OV
DD
(I/O) current and power are primarily dependent on the capacitive loading, frequency, and
utilization of the external buses. The following information provides details about the conditions under which the values in the table
above could be obtained:
a. In general, there would be four PCI devices, an external bus master on the peripheral bus, and external wrap-back on the
Ethernet port. For I
ODD
measurements, PLB = 133.3MHz, OPB = PerClk = 66.6MHz, and PCI = SysClk = 33.3MHz.
b. Typical current and power are characterized at V
DD
= +1.8V, OV
DD
= +3.3V, and T
C
= +36°C while running various
applications under the Linux operating system.
c. Maximum current and power are characterized at V
DD
= +1.9V, OV
DD
= +3.6V, and T
C
= +85°C while running applications
designed to maximize CPU power consumption. An external PCI master heavily loads the PCI bus with transfers targeting
SDRAM while the internal DMA controller further increases SDRAM bus traffic.
2. AV
DD
should be derived from V
DD
using the following circuit:
V
DD
C1
C2
C3
AV
DD
L1
L1 – 2.2μH SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
C1 – 3.3
μF SMT tantalum
C2 – 0.1μF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
C3 – 0.01
μF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
+
AGND
GND