Specifications

PPC405EP – PowerPC 405EP Embedded Processor
36 AMCC
Revision 1.08 – March 24, 2008
Data Sheet
Power
GND
Ground
Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also
thermal balls.
na na na
OV
DD
Output driver voltage—3.3V. na na na
V
DD
Logic voltage—1.8V. na na na
Other pins
Reserved
Reserved pins. Do not make voltage, ground, or signal connections to
these pins.
na na na
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic Symbol Value Unit
Supply Voltage (Internal Logic)
V
DD
0 to +1.95 V
Supply Voltage (I/O Interface)
OV
DD
0 to +3.6 V
PLL Supply Voltage
AV
DD
0 to +1.95 V
Input Voltage (1.8V CMOS receivers)
V
IN
0 to +1.95 V
Input Voltage (3.3V LVTTL receivers)
V
IN
0 to +3.6 V
Input Voltage (5.0V LVTTL receivers)
V
IN
0 to +5.5 V
Storage Temperature Range
T
STG
-55 to +150 °C
Case temperature under bias
T
C
-40 to +120 °C
Note: All specified voltages are with respect to GND.
Table 6. Signal Functional Description (Sheet 6 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name Description I/O Type
Notes