Specifications

PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.08 – March 24, 2008
AMCC 17
Data Sheet
MemAddr00 AB15
SDRAM
Note: During a CAS
cycle MemAddr00 is the least significant bit (lsb) on this bus.
33
MemAddr01 AB16
MemAddr02 AB17
MemAddr03 AA17
MemAddr04 AC18
MemAddr05 AA18
MemAddr06 AC19
MemAddr07 AB19
MemAddr08 Y18
MemAddr09 AA19
MemAddr10 Y19
MemAddr11 AA20
MemAddr12 AC21
MemClkOut0 AA14
SDRAM 33
MemClkOut1 Y13
MemData00 AB12
SDRAM
Note: MemData00 is the most significant bit (msb) on this bus.
33
MemData01 AA12
MemData02 AC11
MemData03 AA11
MemData04 Y11
MemData05 AA10
MemData06 AC9
MemData07 AB9
MemData08 AC8
MemData09 Y09
MemData10 AA8
MemData11 AB7
MemData12 AB6
MemData13 Y07
MemData14 AA6
MemData15 AC5
MemData16 AB5
MemData17 AC4
MemData18 Y05
MemData19 AA4
MemData20 AB3
MemData21 Y03
MemData22 W03
MemData23 V04
MemData24 W02
MemData25 U04
MemData26 V02
MemData27 T04
MemData28 T02
MemData29 R04
MemData30 R03
MemData31 R02
Table 3. Signals Listed Alphabetically (Sheet 5 of 10)
Signal Name Ball Interface Group Page