Specifications

PPC405EP – PowerPC 405EP Embedded Processor
10 AMCC
Revision 1.08 – March 24, 2008
Data Sheet
Serial Interface
• One 8-pin UART and one 2-pin (Tx and Rx only) UART interface provided
• Internal serial clock to allows a wide range of baud rates
• Register compatibility with NS16750 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
IIC Bus Interface
• Compliant with Phillips® Semiconductors I
2
C Specification, dated 1995
• Operation at 100kHz or 400kHz
•8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V
DD
IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses
• All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabil-
ities acts as a GPIO or is used for another purpose.
• Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-
stated if output bit is 1)
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the local PowerPC processor.
Features include:
• Supports seven external and 19 internal interrupts
• Edge-triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to processor core
• Programmable critical interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing