Specifications

ManualsBrandsAMCC ManualsComputer equipmentPPC405

Part Number PPC405EP

Revision 1.08 – March 24, 2008

AMCC 1

PPC405EP

PowerPC 405EP Embedded Processor

Data Sheet

Features

• AMCC PowerPC

405 32-bit RISC processor

core operating up to 333MHz with 16KB D-

and I-caches

• PC-133 synchronous DRAM (SDRAM) inter-

face

- 32-bit interface for non-ECC applications

• 4KB on-chip memory (OCM)

• External peripheral bus

- Flash ROM/Boot ROM interface

- Direct support for 8- or 16-bit SRAM and

external peripherals

- Up to five devices

• DMA support for memory and UARTs.

- Scatter-gather chaining supported

- Four channels

• PCI Revision 2.2 compliant interface (32-bit, up

to 66MHz)

- Asynchronous PCI Bus interface

- Internal or external PCI Bus Arbiter

• Two Ethernet 10/100Mbps (full-duplex) ports

with media independent interface (MII)

• Programmable interrupt controller supports

seven external and 19 internal edge-triggered

or level-sensitive interrupts

• Programmable timers

• Software accessible event counters

• Two serial ports (16750 compatible UART)

• One IIC interface

• General purpose I/O (GPIO) available

• Supports JTAG for board level testing

• Internal processor local bus (PLB) runs at

SDRAM interface frequency

• Supports PowerPC processor boot from PCI

memory

Description

Designed specifically to address embedded

applications, the PowerPC 405EP (PPC405EP)

provides a high-performance, low-power solution that

interfaces to a wide range of peripherals by

incorporating on-chip power management features

and lower power dissipation requirements.

This chip contains a high-performance RISC

processor core, SDRAM controller, PCI bus interface,

Ethernet interface, control for external ROM and

peripherals, DMA with scatter-gather support, serial

ports, IIC interface, and general purpose I/O.

Technology: CMOS SA-27E, 0.18 μm (0.11 μm L

eff

)

Package: 31mm, 385-ball, enhanced plastic ball grid

array (E-PBGA)

Power (typical): 0.72W at 266MHz

Summary of content (51 pages)

PAGE 1
Part Number PPC405EP Revision 1.08 – March 24, 2008 PPC405EP Data Sheet PowerPC 405EP Embedded Processor Features • • • • • • AMCC PowerPC® 405 32-bit RISC processor core operating up to 333MHz with 16KB Dand I-caches PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications 4KB on-chip memory (OCM) External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8- or 16-bit SRAM and external peripherals - Up to five devices DMA support for memory and UARTs.
PAGE 2
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering, PVR, and JTAG Information . . . . . . . . . . . . .
PAGE 3
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet List of Figures PPC405EP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 31mm, 385-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Ordering, PVR, and JTAG Information This section provides the part number nomenclature. For availability, contact your local AMCC sales office.
PAGE 5
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Figure 1.
PAGE 6
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Address Maps The PPC405EP incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EP processor through the use of mtdcr and mfdcr instructions. Table 1.
PAGE 7
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 2.
PAGE 8
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet On-Chip Memory (OCM) The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core.
PAGE 9
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet SDRAM Memory Controller The PPC405EP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to two physical banks. Up to 256MB per bank are supported, up to a maximum of 512MB. Memory timings, address and bank sizes, and memory addressing modes are programmable.
PAGE 10
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.
PAGE 11
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet 10/100 Mbps Ethernet MAC • • Two ports capable of handling full/half duplex 100Mbps and 10Mbps operation Uses the medium independent interface (MII) to the physical layer (PHY not included on chip) JTAG • • • AMCC IEEE 1149.
PAGE 12
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Figure 2. 31mm, 385-Ball E-PBGA Package Top View Logo View Gold Gate Release Corresponds to A01 Ball Location ® PPC405EP 1YWWBZZZZZ 15.5 TYP Lot Number Part Number C Notes: 1. All dimensions are in mm. 2. Package available in leaded and lead-free configurations. 0.20 C 0.25 C A 0.20 31.0 Bottom View AB Y V T 31.0 ± 0.2 P M K H F D B B 27.98 AC 1.
PAGE 13
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Pin Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Shared signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Shared signals appear alphabetically multiple times in the list—once for each signal assigned to the ball.
PAGE 14
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3.
PAGE 15
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3.
PAGE 16
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3.
PAGE 17
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3.
PAGE 18
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3.
PAGE 19
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3.
PAGE 20
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 8 of 10) Signal Name PCIReq0/Gnt Ball Interface Group Page E20 PCIReq1 F20 PCIReq2 E22 PCIReset G20 PCI 31 PCISErr J20 PCI 31 PCIStop G22 PCI 31 PCITRDY G21 PCI 31 [PerAddr03]GPIO14 B04 [PerAddr04]GPIO15 A04 External Slave Peripheral Note: PerAddr3 is the most significant bit (msb) on this bus.
PAGE 21
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3.
PAGE 22
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 3.
PAGE 23
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 4.
PAGE 24
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 4.
PAGE 25
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 4.
PAGE 26
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 4.
PAGE 27
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 4.
PAGE 28
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 4.
PAGE 29
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Signal List The following table provides a summary of the number of package pins associated with each functional interface group. Table 5. Pin Summary Group No.
PAGE 30
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Unused I/Os Strapping of some pins may be necessary when they are unused. Although the PPC405EP requires only the pullup and pull-down terminations as specified in the “Signal Functional Description” on page 31, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive.
PAGE 31
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 6. Signal Functional Description (Sheet 1 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6.
PAGE 32
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 6. Signal Functional Description (Sheet 2 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6.
PAGE 33
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 6. Signal Functional Description (Sheet 3 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6.
PAGE 34
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 6. Signal Functional Description (Sheet 4 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6.
PAGE 35
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 6. Signal Functional Description (Sheet 5 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6.
PAGE 36
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 6. Signal Functional Description (Sheet 6 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6.
PAGE 37
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 8. Package Thermal Specifications The PPC405EP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the EPBGA packages in a convection environment are as follows: Package—Thermal Resistance Airflow ft/min (m/sec) Symbol Unit 0 (0) 100 (0.51) 200 (1.02) 31mm, 385-balls—Junction-to-Case θJC 2 2 2 °C/W 31mm, 385-balls—Case-to-Ambient1 θCA 17.8 16.
PAGE 38
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Table 9. Recommended DC Operating Conditions (Sheet 2 of 2) Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications. 2. See “5V-Tolerant Input Current” on page 39.
PAGE 39
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Figure 3. 5V-Tolerant Input Current 50 0 -50 -100 Input Current (μA) -150 -200 -250 -300 -350 0.0 1.0 2.0 3.0 4.0 5.0 Input Voltage (V) Table 10. Input Capacitance Parameter Symbol Maximum Unit 3.3V LVTTL I/O CIN1 12 pF 5V tolerant, 3.3V LVTTL I/O CIN2 12 pF PCI I/O CIN3 12 pF Rx only pins CIN4 9 pF IIC pads CIN5 6.
PAGE 40
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 11. DC Electrical Characteristics Parameter Symbol Minimum Typical Maximum Unit Active Operating Current (VDD)–266MHz IDD 300 610 mA Active Operating Current (VDD)–333MHz IDD 325 690 mA Active Operating Current (OVDD) IODD 45 200 mA PLL VDD Input current IPLL 16 23 mA Active Operating Power–266 MHz PDD 0.72 1.92 W Active Operating Power–333MHz PDD 0.76 2.07 W Note: 1.
PAGE 41
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table “Recommended DC Operating Conditions.” For all signals other than PCI signals, AC specifications are characterized at OVDD = 3V and TC = 85°C with the 50pF test load shown in the figure at right.
PAGE 42
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 12. Clocking Specifications Symbol Parameter Min Max Units 133.33, 200, 266.66, or 333.33 MHz CPU PFC Processor clock frequency PTC Processor clock period 7.5, 5, 3.75 or 3 ns SysClk Input SCFC Frequency 25 100 MHz SCTC Period 10 40 ns SCTCS Edge stability (phase jitter, cycle to cycle) – ±0.
PAGE 43
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405EP. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency.
PAGE 44
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 13. Peripheral Interface Clock Timings Parameter Min Max Units Note 1 66.66 MHz 15 Note 1 ns PCIClk input high time 40% of nominal period 60% of nominal period ns PCIClk input low time 40% of nominal period 60% of nominal period ns – 2.
PAGE 45
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Figure 5. Input Setup and Hold Timing Waveform System Clock 1.5V TIS TIH MIN MIN Inputs 1.5V Valid Figure 6. Output Delay and Float Timing Waveform System Clock 1.5V TOH MIN TOV MAX Outputs 1.5V Valid TOF Outputs AMCC MAX MIN 1.
PAGE 46
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 14. I/O Specifications—Group 1 (Sheet 1 of 2) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual. 3.
PAGE 47
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 14. I/O Specifications—Group 1 (Sheet 2 of 2) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual. 3.
PAGE 48
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Table 15. I/O Specifications—Group 2 Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS model (available from www.
PAGE 49
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Initialization The following describes the method by which initial chip settings are established when a system reset occurs. Strapping When the SysReset input is driven low (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405EP start-up. The actual capture instant is the nearest system clock edge before the deassertion of reset.
PAGE 50
Revision 1.08 – March 24, 2008 PPC405EP – PowerPC 405EP Embedded Processor Data Sheet Document Revision History 50 Revision Date Description 1.01 07/30/04 Initial Release 1.02 01/10/05 Add lead-free part numbers and clean up AMCC conversion. 1.03 05/01/07 Add information on connection of target device IDSEL to the addess bus. Modify description of TRST signal. Remove note on TrcClk concerning initilization. 1.04 06/01/07 Update package thickness values (package drawing).
PAGE 51
PPC405EP – PowerPC 405EP Embedded Processor Revision 1.08 – March 24, 2008 Data Sheet Applied Micro Circuits Corporation 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601 http://www.amcc.com AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet.