Specifications

405GP – Power PC 405GP Embedded Processor
8 AMCC
Revision 2.01 – January 6, 2005
Data Sheet
DCR Address Map 4KB Device Configuration Registers
Function Start Address End Address Size
Total DCR Address Space
1
0x000 0x3FF
1KW (4KB)
1
By function:
Reserved 0x000 0x00F 16W
Memory Controller Registers 0x010 0x011 2W
External Bus Controller Registers 0x012 0x013 2W
Decompression Controller Registers 0x014 0x015 2W
Reserved 0x016 0x017 2W
On-Chip Memory Controller Registers 0x018 0x01F 8W
Reserved 0x020 0x07F 96W
PLB Registers 0x080 0x08F 16W
Reserved 0x090 0x09F 16W
OPB Bridge Out Registers 0x0A0 0x0A7 8W
Reserved 0x0A8 0x0AF 6W
Clock, Control, and Reset 0x0B0 0x0B7 8W
Power Management 0x0B8 0x0BF 8W
Interrupt Controller 0x0C0 0x0CF 16W
Reserved 0x0D0 0x0FF 48W
DMA Controller Registers 0x100 0x13F 64W
Reserved 0x140 0x17F 64W
Ethernet MAL Registers 0x180 0x1FF 128W
Reserved 0x200 0x3FF 512W
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register, or 1 kiloword (KW) (which equals 4 KB).