Specifications

405GP – Power PC 405GP Embedded Processor
6 AMCC
Revision 2.01 – January 6, 2005
Data Sheet
PPC405GP Embedded Controller Functional Block Diagram
The PPC405GP is designed using the IBM
®
Microelectronics Blue Logic
TM
methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect
TM
Bus Architecture.
PPC405
Processor Core
DOCM
IOCM
DCU
ICU
OCM
Control
OCM
SRAM
DCR Bus
16KB
On-chip Peripheral Bus (OPB)
GPIO
IIC UART UART
MAL Ethernet
DMA
Bridge
Processor Local Bus (PLB)
SDRAM
PCI Bridge
Code
Decompression
External
Bus
Controller
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
MII
Controller
OPB
Interrupt
Controller
Arb
32-bit addr
32-bit data
13-bit addr
32-bit data
External
Bus Master
Controller
Universal
I-Cache
D-Cache
(4-Channel)
(CodePack™)
66 MHz max (async)
DCRs
33 MHz max (sync)
8KB
Arb