Specifications

405GP – Power PC 405GP Embedded Processor
AMCC 43
Revision 2.01 – January 6, 2005
Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device
Characteristic Symbol Value Unit
Supply Voltage (Internal Logic)
V
DD
0 to +2.7 V
Supply Voltage (I/O Interface)
OV
DD
0 to +3.6 V
PLL Supply Voltage
AV
DD
0 to +2.7 V
Input Voltage (2.5V CMOS receivers)
V
IN
-0.6 to V
DD
+ 0.6
V
Input Voltage (3.3V LVTTL receivers)
V
IN
-0.6 to OV
DD
+ 0.6
V
Input Voltage (5.0V LVTTL receivers)
V
IN
-0.6 to OV
DD
+ 2.4
V
Storage Temperature Range
T
STG
-55 to +150 °C
Case temperature under bias
T
C
-40 to +120 °C
Notes:
4. All specified voltages are with respect to GND.
Package Thermal Specifications
The PPC405GP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the
E-PBGA packages (leaded and lead-free) in a convection environment are as follows:
Package—Thermal Resistance
Symbol
Airflow
ft/min (m/sec)
Unit
0 (0) 100 (0.51) 200 (1.02)
35mm, 456-balls—Junction-to-Case
θ
JC
222°C/W
35mm, 456-balls—Case-to-Ambient
1
θ
CA
14 13 12 °C/W
27mm, 456-balls—Junction-to-Case
θ
JC
222°C/W
27mm, 456-balls—Case-to-Ambient
1
θ
CA
18 16 15 °C/W
25mm, 413-balls—Junction-to-Case
θ
JC
1.5 1.5 1.5 °C/W
25mm, 413-balls—Case-to-Ambient
1
θ
CA
17 15 13 °C/W
Notes:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, T
C
, is measured at top center of case surface with device soldered to circuit board.
b. T
A
= T
C
– P×θ
CA
, where T
A
is ambient temperature and P is power consumption.
c. T
CMax
= T
JMax
– P×θ
JC
, where T
JMax
is maximum junction temperature and P is power consumption.