Specifications

405GP – Power PC 405GP Embedded Processor
40 AMCC
Revision 2.01 – January 6, 2005
Data Sheet
UART1_Tx UART1 Serial Data Out. O
5V tolerant
3.3V LVTTL
6
UART1_DSR
/
UART1_CTS
UART1 Data Set Ready
or
UART1 Clear To Send. To access this function, software must toggle
a DCR bit.
I
5V tolerant
3.3V LVTTL
1
UART1_R
TS/
UART1_DTR
UART1 Request To Send
or
UART1 Data Terminal Ready. To access this function, software must
toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
6
IICSCL IIC Serial Clock. I/O
5V tolerant
3.3V LVTTL
1, 2
IICSDA IIC Serial Data. I/O
5V tolerant
3.3V LVTTL
1, 2
Interrupts Interface
IRQ0:6[GPIO17:23]
Interrupt requests
or
General Purpose I/O. To access this function, software must toggle a
DCR bit.
I[I/O]
5V tolerant
3.3V LVTTL
1
JTAG Interface
TDI Test data in. I
5V tolerant
3.3V LVTTL
1, 4
TMS JTAG test mode select. I
5V tolerant
3.3V LVTTL
1, 4
TDO Test data out. O
5V tolerant
3.3V LVTTL
TCK
JTAG test clock. The frequency of this input can range from DC to
25MHz.
I
5V tolerant
3.3V LVTTL
1, 4
TRST
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405GP.
I
5V tolerant
3.3V LVTTL
5
System Interface
SysClk Main system clock input. I
5V tolerant
3.3V LVTTL
SysReset
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
I/O
5V tolerant
3.3V LVTTL
1, 2
AV
DD
Clean voltage input for the PLL. I
SysErr Set to 1 when a Machine Check is generated. O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger. I
5V tolerant
3.3V LVTTL
1, 2
Signal Functional Description (Part 6 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name Description I/O Type
Notes