Specifications

405GP – Power PC 405GP Embedded Processor
AMCC 33
Revision 2.01 – January 6, 2005
Data Sheet
Signal List
The following table provides a summary of the number of package pins associated with each functional interface
group.
Multiplexed Pins
In the table “Signal Functional Description” on page 35, each external signal is listed along with a description of the
signal function. Some signals are multiplexed on the same pin (ball) so that the pin can be used for different
functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for
example, GPIO1[TS1E]). Active-low signals (for example, RAS
) are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same function.
The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address
pins are used as outputs by the PPC405GP to broadcast an address to external slave devices when the
PPC405GP has control of the external bus. When, during the course of normal chip operation, an external master
gains ownership of the external bus, these same pins are used as inputs which are driven by the external master
and received by the EBC in the PPC405GP. In this example, the pins are also bidirectional, serving as both inputs
and outputs.
Intialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 55). Note that the
use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
Pin Summary
Group
No. of Pins
413-Ball package 456-Ball Package
25 mm 35 mm 27mm
PCI606060
Ethernet 18 18 18
SDRAM717171
External peripheral 96 96 96
External master 9 9 9
Internal peripheral 15 15 15
Interrupts 7 7 7
JTAG555
System 19 19 19
Total Signal Pins 300 300 300
OV
DD
38 32 24
V
DD
22 24 24
Gnd266056
Thermal (and Gnd) 15 36 36
Reserved 12 4 16
Total Pins 413 456 456