Specifications

405GP – Power PC 405GP Embedded Processor
AMCC 25
Revision 2.01 – January 6, 2005
Data Sheet
Reserved
B19
C16
D18
E2
H3
T21
V20
V21
W22
Y5
1
AA8
AB5
A19
2
B17
3
C13
3
D20
H1
2
K2
3
N24
3
P3
3
U25
3
W26
2
Y23
Y26
AF4
1
AF8
2
AD14
3
AE10
3
Other
Notes:
1. Y5 (on the 413-ball package) and AF4 must be tied to OV
DD
or GND.
All other reserved pins should be left unconnected.
2. Reserved on 27mm package. GND on 35mm package.
3. Reserved on 27mm package. OV
DD
on 35mm package.
42
SysClk H16 A25 System 40
SysErr P14 AD25 System 40
SysReset
J15 D22 System 40
TCK U16 AD22 JTAG 40
TDI U13 AE24 JTAG 40
TDO T13 AD23 JTAG 40
TestEn
E20 D26 System 40
TmrClk L16 D24 System 40
TMS U17 AC22 JTAG 40
[TrcClk]GPIO9 T7 AB3 System 40
TRST
T16 AE26 JTAG 40
[TS1E]GPIO1
[TS2E]GPIO2
[TS1O]GPIO3
[TS2O]GPIO4
[TS3]GPIO5
[TS4]GPIO6
[TS5]GPIO7
[TS6]GPIO8
A20
C19
A21
AB18
AC4
AB4
AC3
Y6
D18
C20
A22
AF18
AC9
AE8
AF5
AC7
Trace 41
UART0_CTS
U7 AB4 Internal Peripheral 39
UART0_DCD
AA17 AE18 Internal Peripheral 39
UART0_DSR
P10 AE3 Internal Peripheral 39
UART0_DTR
T8 AF2 Internal Peripheral 39
UART0_RI
AC16 AD15 Internal Peripheral 39
UART0_RTS
AB15 AD16 Internal Peripheral 39
UART0_Rx AA14 AE16 Internal Peripheral 39
UART0_Tx U8 AF3 Internal Peripheral 39
UART1_CTS
/UART1_DSR
N8
AC3 Internal Peripheral 39
UART1_DSR
/UART1_CTS
N8
AC3 Internal Peripheral 39
UART1_DTR
/UART1_RTS
N7
AD2 Internal Peripheral 39
UART1_RTS
/UART1_DTR
N7
AD2 Internal Peripheral 39
UART1_Rx W4 AC1 Internal Peripheral 39
UART1_Tx N3 AC2 Internal Peripheral 39
UARTSerClk Y14 AE17 Internal Peripheral 39
Signals Listed Alphabetically (Part 9 of 10)
Signal Name 413-Ball 456-Ball Interface Group Page