Specifications
405GP – Power PC 405GP Embedded Processor
24 AMCC
Revision 2.01 – January 6, 2005
Data Sheet
PerData0
PerData1
PerData2
PerData3
PerData4
PerData5
PerData6
PerData7
PerData8
PerData9
PerData10
PerData11
PerData12
PerData13
PerData14
PerData15
PerData16
PerData17
PerData18
PerData19
PerData20
PerData21
PerData22
PerData23
PerData24
PerData25
PerData26
PerData27
PerData28
PerData29
PerData30
PerData31
R3
W1
U2
T2
U1
P2
N2
M3
R1
M2
P1
M1
K1
J1
L2
M8
H1
K2
L3
G1
G2
J2
H2
F2
E1
J3
G3
D1
J4
F3
D2
H4
U4
U3
U1
T4
R2
P4
R4
P2
R1
P1
N3
N1
M1
N2
M3
M4
N4
M2
L3
L4
K1
L2
K3
J1
K4
J3
J2
J4
H3
G1
H2
H4
External Slave Peripheral
Note: PerData0 is the most significant bit (msb) on this bus.
37
PerErr H8 B1 External Master Peripheral 39
PerOE
K10 C2 External Slave Peripheral 37
PerPar0
PerPar1
PerPar2
PerPar3
L7
F4
E3
C1
D3
G4
G3
E1
External Slave Peripheral 37
PerReady L8 E3 External Slave Peripheral 37
PerR/W
H7 C1 External Slave Peripheral 37
PerWBE0
PerWBE1
PerWBE2
PerWBE3
D4
B2
B1
E4
D2
E2
F4
D1
External Slave Peripheral 37
[PerWE
]PCIINT G13 C23 External Slave Peripheral 37
PHYCol
Y21
AA25 Ethernet 36
PHYCrS
T20
W23 Ethernet 36
PHYRxClk
AA18
AF20 Ethernet 36
[PHYMDIO]EMCMDIO
T17
AD26 Ethernet 36
PHYRxD0
PHYRxD1
PHYRxD2
PHYRxD3
AA13
Y19
Y18
Y17
AE23
AF23
AC20
AD20
Ethernet 36
PHYRxDV R21 V24 Ethernet 36
PHYRxErr T22 U24 Ethernet 36
PHYTxClk C21 E25 Ethernet 36
RAS
R12 AF24 SDRAM 37
RcvrInh L17 C25 System 40
[R
eq]PCIGnt0 W23 U23 PCI 35
Signals Listed Alphabetically (Part 8 of 10)
Signal Name 413-Ball 456-Ball Interface Group Page