Specifications

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Part Number 405GP

Revision 2.01 – January 6, 2005

AMCC 1

405GP

Power PC 405GP Embedded Processor

Data Sheet

Features

•PowerPC

405 32-bit RISC processor core

operating up to 266MHz

• Synchronous DRAM (SDRAM) interface operating

up to 133MHz

- 32-bit interface for non-ECC applications

- 40-bit interface serves 32 bits of data plus 8

check bits for ECC applications

• 4KB on-chip memory (OCM)

• External peripheral bus

- Flash ROM/Boot ROM interface

- Direct support for 8-, 16-, or 32-bit SRAM and

external peripherals

- Up to eight devices

- External Mastering supported

• DMA support for external peripherals, internal

UART and memory

- Scatter-gather chaining supported

- Four channels

• PCI Revision 2.2 compliant interface (32-bit, up to

66MHz)

- Synchronous or asynchronous PCI Bus

interface

- Internal or external PCI Bus Arbiter

• Ethernet 10/100Mbps (full-duplex) support with

media independent interface (MII)

• Programmable interrupt controller supports seven

external and 19 internal edge triggered or level-

sensitive interrupts

• Programmable timers

• Two serial ports (16550 compatible UART)

• One IIC interface

• General purpose I/O (GPIO) available

• Supports JTAG for board level testing

• Internal processor local Bus (PLB) runs at SDRAM

interface frequency

• Supports PowerPC processor boot from PCI

memory

Description

Designed specifically to address embedded

applications, the PowerPC 405GP (PPC405GP)

provides a high-performance, low-power solution that

interfaces to a wide range of peripherals by

incorporating on-chip power management features

and lower power dissipation requirements.

This chip contains a high-performance RISC

processor core, SDRAM controller, PCI bus interface,

Ethernet interface, control for external ROM and

peripherals, DMA with scatter-gather support, serial

ports, IIC interface, and general purpose I/O.

Technology: CMOS SA-12E, 0.25 µm

(0.18 µm L

eff

)

Package: 456-ball (35mm or 27mm), or 413-ball

(25mm) enhanced plastic ball grid array (E-PBGA)

Power (typical): TBDW at 133MHz, 1.5W at 200MHz,

2W at 266MHz

Summary of content (58 pages)

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Part Number 405GP Revision 2.01 – January 6, 2005 405GP Data Sheet Power PC 405GP Embedded Processor Features • PowerPC® 405 32-bit RISC processor core operating up to 266MHz • Synchronous DRAM (SDRAM) interface operating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications • 4KB on-chip memory (OCM) • External peripheral bus • PCI Revision 2.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Contents Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Revision 2.01 – January 6, 2005 Data Sheet 405GP – Power PC 405GP Embedded Processor Figures PPC405GP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 25mm, 413-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 27mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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05GP – Power PC 405GP Embedded Processor Revision 2.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Address Map Support The PPC405GP incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GP processor through the use of mtdcr and mfdcr instructions.
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405GP – Power PC 405GP Embedded Processor Revision 2.
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Revision 2.01 – January 6, 2005 Data Sheet 405GP – Power PC 405GP Embedded Processor On-Chip Memory (OCM) The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet • Supports PCI target access to all PLB address spaces • Supports PowerPC processor boot from PCI memory SDRAM Memory Controller The PPC405GP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four physical banks. Up to 256MB per bank are supported, up to a maximum of 1GB.
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Revision 2.01 – January 6, 2005 Data Sheet 405GP – Power PC 405GP Embedded Processor Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor.
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Revision 2.01 – January 6, 2005 405GP – Power PC 405GP Embedded Processor Data Sheet 25mm, 413-Ball E-PBGA Package Top View A1 ball corner 15.7 MAX C Note: All dimensions are in mm. 0.20 C 0.25 C 0.20 0.35 C 25.0 Bottom View 22.0 2.223 REF AB Y V T 25.0 P M K H F D AC 1.00 AA W Thermal balls GLOB TOP U R N L J G E C B A B 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 A 14 ∅ 0.635 SOLDER BALL x 413 ∅ 0.30 M C A B ∅ 0.10 M C 0.5 ± 0.1 TYP 0.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet 27mm, 456-Ball E-PBGA Package Reserved Area for Ejector Pin Mark x 4 TYP Corner Shape is Chamferred or Rounded Top View Gold Gate Release Corresponds to A1 Ball Location 24 TYP C Notes: 1. All dimensions are in mm. 2. This package is available in leaded or lead-free configurations. 0.20 C A 0.20 0.25 C 27.0 AF AD AB Y V T 27.0 P M K H F D 0.35 C 25.0 Bottom View 1.
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Revision 2.01 – January 6, 2005 405GP – Power PC 405GP Embedded Processor Data Sheet 35mm, 456-Ball E-PBGA Package Reserved Area for Ejector Pin Mark x 4 TYP Corner Shape is Chamferred or Rounded Top View Gold Gate Release Corresponds to A1 Ball Location 30.0 Typ C Notes: 1. All dimensions are in mm. 2. This package is available in leaded or lead-free configurations. 0.20 C A 0.20 0.25 C 35.0 AF AD AB Y V T 35.0 P M K H F D 0.35 C 31.75 Bottom View 1.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Pin Lists The PPC405GP embedded controller is available as a 456-ball or a 413-ball E-PBGA. The 456-ball package is available in two sizes—35 millimeters and 27 millimeters. The 413-ball package size is 25 millimeters. In this section there are three tables that correlate the external signals to the physical package pin (ball) on which they appear.
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405GP – Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name Revision 2.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signals Listed Alphabetically Signal Name (Part 3 of 10) 413-Ball 456-Ball AB9 AB13 AB14 AB18 AB22 AC4 AC23 AD3 AD24 AE1 AE2 AE25 AF1 AF6 AF81 AF11 AF16 AF21 AF25 AF26 GND Interface Group Page Ground Notes: 1. Reserved on 27mm package. GND on 35mm package. 2. On the 456-ball packages, L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also thermal balls. 3.
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405GP – Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name Revision 2.
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405GP – Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name Revision 2.
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405GP – Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 Data Sheet (Part 8 of 10) 413-Ball 456-Ball R3 W1 U2 T2 U1 P2 N2 M3 R1 M2 P1 M1 K1 J1 L2 M8 H1 K2 L3 G1 G2 J2 H2 F
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signals Listed Alphabetically Signal Name Reserved (Part 9 of 10) 413-Ball 456-Ball B19 C16 D18 E2 H3 T21 V20 V21 W22 Y51 AA8 AB5 A192 B173 C133 D20 H12 K23 N243 P33 U253 W262 Y23 Y26 AF41 AF82 AD143 AE103 Interface Group Page Other Notes: 1. Y5 (on the 413-ball package) and AF4 must be tied to OVDD or GND. All other reserved pins should be left unconnected. 2. Reserved on 27mm package. GND on 35mm package. 3.
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405GP – Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name VDD WE 26 Revision 2.
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405GP – Power PC 405GP Embedded Processor Revision 2.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signal List The following table provides a summary of the number of package pins associated with each functional interface group. Pin Summary No.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3kΩ to +3.3V (10kΩ to +5V can be used on 5V tolerant I/Os) and pull-down value of 1kΩ to GND, applies only to individually terminated signals.
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Revision 2.01 – January 6, 2005 Data Sheet 405GP – Power PC 405GP Embedded Processor Signal Functional Description (Part 1 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 4.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signal Functional Description (Part 2 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 4.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signal Functional Description (Part 3 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 4.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signal Functional Description (Part 4 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 4.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signal Functional Description (Part 5 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 4.
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5GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signal Functional Description (Part 6 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 4.
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Revision 2.01 – January 6, 2005 Data Sheet 405GP – Power PC 405GP Embedded Processor Signal Functional Description (Part 7 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 4.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Signal Functional Description (Part 8 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values. 4.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device Characteristic Symbol Value Unit Supply Voltage (Internal Logic) VDD 0 to +2.7 V Supply Voltage (I/O Interface) OVDD 0 to +3.6 V PLL Supply Voltage AVDD 0 to +2.7 V Input Voltage (2.5V CMOS receivers) VIN -0.6 to VDD + 0.
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Revision 2.01 – January 6, 2005 405GP – Power PC 405GP Embedded Processor Data Sheet Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications. 2. See “5V-Tolerant Input Current” on page 45. Parameter Symbol Minimum Typical Maximum Unit VDD 2.3 2.5 2.7 V I/O Supply Voltage OVDD 3.0 3.3 3.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet 5V-Tolerant Input Current 100 0 Input Current (µA) -100 -200 -300 -400 -500 -600 -700 0.0 1.0 2.0 3.0 4.0 5.0 Symbol Maximum Unit 3.3V LVTTL I/O CIN1 5.
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Revision 2.01 – January 6, 2005 Data Sheet 405GP – Power PC 405GP Embedded Processor Clocking Specifications Symbol Parameter Min Max Units 133.33/200/266.66 MHz CPU PFC Processor clock frequency PTC Processor clock period 7.5/5/3.75 ns SysClk Input SCFC Clock input frequency 25 66.66 MHz SCTC Clock period 15 40 ns SCTCS Clock edge stability (phase jitter, cycle to cycle) ± 0.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405GP. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency.
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Revision 2.01 – January 6, 2005 Data Sheet 405GP – Power PC 405GP Embedded Processor Peripheral Interface Clock Timings Parameter Min Max Units Note 1 66.66 MHz PCIClk period (asynchronous mode) 15 Note 1 ns PCI Clock frequency (synchronous mode) 25 33.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Notes: 1. In all of the following I/O Specifications tables a timing values of “na” means “not applicable” and “dc” means “don’t care.” 2. See “Test Conditions” on page 46 for output capacitive loading. I/O Specifications—All speeds (Part 1 of 2) Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
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Revision 2.01 – January 6, 2005 405GP – Power PC 405GP Embedded Processor Data Sheet I/O Specifications—All speeds (Part 2 of 2) Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I/O H is specified at 0.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet I/O Specifications—133 and 200MHz Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP IBIS model (available from www.amcc.
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Revision 2.01 – January 6, 2005 405GP – Power PC 405GP Embedded Processor Data Sheet I/O Specifications—266MHz Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP IBIS model (available from www.amcc.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Strapping When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions.
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Revision 2.01 – January 6, 2005 Data Sheet 405GP – Power PC 405GP Embedded Processor Printed in the United States of America, January 2005 The following are trademarks of AMCC in the United States, or other countries, or both: AMCC Other company, product, and service names may be trademarks or service marks of others.
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405GP – Power PC 405GP Embedded Processor Revision 2.01 – January 6, 2005 Data Sheet Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet.