Specifications

Typical Experiment
76
clears the dwell latch, 2/2 U603, raising !COUNT
high again. This also resets and enables the dwell
counters in U1308 to count down the programmed
dwell time. During the first 1 ms of the dwell time,
the processor is reading and resetting the counters,
reloading the T counter, and updating any scanned
parameters. When the processor is finished, it
strobes !T_REARM low which resets the timeout
latch. When the dwell timer times out, the Q
output of 2/3 U1308 goes low which clocks the
dwell latch and counting begins again.
If the dwell mode is external, the output of the
dwell timer is always low and the EXT START
INPUT clocks the start latch to start the next count
period. 1/4 U601 disables the start latch while
counting is in progress and is not re-enabled until
the processor is finished servicing the counters.
The EXT STOP INPUT clocks the stop latch, 2/2
U603 if the counters have previously been started.
The stop latch asserts !STOP which terminates the
TIMER pulse and generates a TIMEOUT signal.
The DWELL OUTPUT is driven from the dwell
latch via Q601 and Q602. This output is high
between count periods. The minimum output low
pulse width is 100 ns even if the preset condition
is shorter.
GATE GENERATORS
The gates are generated using four programmable
delay generators, one for each delay and one for
each width. Each delay can range from 10 ns to 1
s. Each delay is made up of a 4 MHz counter and
an analog delay which covers 250 ns. To program
a delay, the appropriate number of oscillator
clocks (250 ns) are loaded into the counter and the
remainder (<250 ns) is programmed into the
analog delay. All counters and analog delays are
hardware reset when they terminate to give a 1
MHz retrigger rate.
The following discussion focuses on the A GATE
delay. B GATE delay and both gate widths are
similar.
DIGITAL DELAY (sheet 8)
The discriminated trigger input clocks the trigger
latch, 2/2 U405. The output of the trigger latch is
converted to the TTL signal, DLY_ENA.
DLY_ENA starts the 4 MHz delay oscillator. The
output of this oscillator is phase coherent with the
gate trigger.
The delay oscillator is a TTL oscillator comprising
U803 and U801. U803 is a fast TTL comparator
with U801 as an output buffer. The RC feedback
network of R810 and C806 sets the frequency.
U801 is used as the buffer since HC gates have
output swings which are not temperature
dependent but follow their power supply voltages.
The +5V power for this oscillator is derived from
the precision +10.000V reference, U1505. 1/2
U802 and Q801 form a precision, low drift +5V
regulator. This results in a temperature stable
frequency.
The frequency may be adjusted slightly by
changing the analog voltage DLY_FREQ. 2/2
U802 and Q802 form a current source to
differential pair Q803 and Q804. Q803 and Q804
switch this current from ground to C806. When
U801 is discharging C806, Q803 will be charging
C806. Thus the half cycle when C806 is high can
be lengthened by changing the DLY_FREQ
voltage and the frequency adjusted by the
processor. The proper DLY_FREQ voltage is
determined at the factory and stored in the ROM.
This provides automated calibration of the delay
clock.
The 4 MHz signal is counted by 1/3 and 2/3 of
U1307. When the programmed number of cycles
have been counted, the output of 2/4 U805 goes
low. The next clock pulse clocks the latch 1/2
U804 to generate !DLYA_TIMEOUT which
signals the end of the digital portion of the delay.
The line !DLYA_COUNT0 is asserted low when
no digital delay is required (short delays).
ANALOG DELAY (sheet 7)
The analog delay is determined by charging the
capacitor C706 with the constant current source
Q701. The constant current source is programmed
by D/A voltage DLYA_SLOPE and is calibrated