Specifications

SR400 Circuit Description
75
from INPUT 1 and the signal A10MHZ_INH
disables input from the 10 MHz timebase. The
selected input is buffered by 4/4 of U301 to drive
the A_DISC output drivers, Q301 and Q302.
When both inputs to 1/4 of U301, !A_GATE and
!TIMER are both low, the counter is enabled.
(!SIGNAL means NOT_SIGNAL or
SIGNAL_BAR) !TIMER is low the duration of
the count period as determined by the preset
condition. !A_GATE is low when the A gate is
active. !A_GATE is always low if A gate is CW.
Thus only those gates which fall within the timer
count period enable counting. 1/2 U302 is the gate
multiplier. If a rising edge from the input source
clocks 1/2 U302 while !A_GATE and !TIMER are
both low, then a 2 ns positive pulse will appear at
the Q output. This ensures that only leading edges
of the input that occur during the gate are counted.
2/2 U302 and 1/2 U303 are divide by 2 flip flops
and are the low 2 bits of the counter. 1/4 and 2/4
of U307 translate their outputs to TTL levels.
U304 is a FAST TTL divide by 16 counter which
counts the output of the ECL flip flops. 1/4 and
2/4 of U307 and U304 comprise the low 6 bits
(/64) of the counter. Their outputs can be read by
the processor via U1301. The last bit of U304 then
clocks 1/3 U1305, an 8253 counter. This counter is
programmed to divide by 6250. Its output then
interrupts the processor and the highest bits of the
count are updated within the processor. The signal
!RST_TTL clears all the counters to zero. LOAD
preclocks the 8253 after !RST_TTL to preload the
counter. The counter is reset at the end of each
count period.
The input to counter B is always B_PULSE and is
buffered by 2/3 U305 to drive the B_DISC output
driver. The counter is enabled when !B_GATE
and !TIMER are both low. !TIMER may be forced
low by B_SET in the case when B counter is
preset. In this case, the B counter is still gated by
!B_GATE. The rest of B counter is identical to A
counter.
T COUNTER (sheets 4 and 5)
The input to counter T is selected by U401 and can
be the 10 MHz timebase, the gate trigger, the
output of the T discriminator, or B_PULSE X
B_GATE (when B is preset). Note that only
counter T is presettable and when B is selected to
be preset, counter B's input is routed to counter T.
3/3 U305 buffers the input and drives the T_DISC
output. TDISC_INH inhibits the T DISC output
when B is preset. Counter T is in a timer
configuration. 1/2 U402, U403, FAST TTL
counter U404 and the 3 counters in U1304
comprise the T counter. The low 6 bits are preset
by CT0-CT6. U1304 is preset by the processor
loading the counters. Counter T is preset to the
programmed TSET or BSET number at the end of
each count period. When !COUNT goes low, the
next rising edge from the input will clock 2/2
U402 starting the TIMER or count period. The
ECL counter 1/2 U402 is then enabled to count.
Counting continues until the preset number of
counts have occurred and all inputs to 2/2 U406
are low. When this happens, 1/2 U405 latches this
condition and terminates the TIMER pulse from
2/2 U402. The TIMER pulse thus lasts for the
preset number of pulse periods from the input.
Note that counting does not begin until the first
pulse after !COUNT goes low. The end of the
TIMER pulse generates TIMEOUT which signals
that counting has halted and the counters may be
read. The processor can use the !STOP to halt
counting at any time.
START/STOP AND DWELL (sheet 6)
U605 is a 20 MHz crystal oscillator and is the
timebase for the entire instrument. The output of
U605 directly clocks the processor. U602 provides
10 MHz to the counters and 5 MHz to the dwell
timer and GPIB controller.
2/3 and 3/3 of U1308 make up the dwell timer.
Assuming that the counters have been reset, the Q
output of 2/3 U1308 will be low and the !Q output
of the start latch, 1/2 U604, will be high. When the
START key is pressed or a CS command is
received, the processor asserts !CPU_START
which sets !Q of the start latch low. An
EXTERNAL START INPUT does the same thing.
!Q going low clocks the dwell latch, 2/2 U603, so
that its Q output goes high. This in turn sets
!COUNT low and the count period begins. When
the preset condition is met and the TIMER pulse
terminates, the TIMEOUT signal clocks the
timeout latch, 1/2 U501. The timeout latch
interrupts the processor indicating that counters A
and B have valid data. The timeout latch also