Specifications

Typical Experiment
74
are 2 address lines, chip select, power and ground,
and display contrast control.
The electroluminescent backlight requires a 100
Vac, 100 Hz signal. This power is derived from
the dc power supplies and is isolated from the ac
main.
The status LED indicators are driven by U1405.
The key pad is strobed by U1405 and read by
U1303.
DIGITAL TO ANALOG CONVERTER
(sheet 15)
U1502 is a 12-bit D/A converter which is loaded 4
bits at a time by the processor. The voltage output
from 4/4 U1504 is 0 to -10.24 Vdc. The rest of
U1504 shifts and attenuates this output to provide
control voltages. These analog outputs are
multiplexed onto 20 sample and hold amplifiers.
Each S/H is refreshed every 2 ms.
U1503 multiplexes the gate generator calibration
voltages. U1506 multiplexes the gate adjustment
voltages as well as the analog outputs and the
LCD contrast. U1501 provides the discriminator
thresholds.
FAST COUNTERS
SIGNAL INPUTS (sheet 1)
Signal inputs INPUT 1 and INPUT 2 pass through
amplifiers AMP 1 and AMP 2. These are dc to 300
MHz, gain of 5 amplifiers. They have a 1.2 ns
rise/fall time, ± 300 mV input range, and a 4 ns
recovery time from a 20X overload. The inputs are
protected to ± 5Vdc and ± 50V transients.
The following is a brief description of amplifier
AMP 1. AMP 2 is identical. R102, R103, R104,
P101, D101, D102, and D103 comprise an
overload protection circuit which clamps the
inputs to the amplifiers at ± .35 V. Ac gain is
provided by Q101 and Q102 and is compensated
by C107. U101 sets the amplifier's dc gain. Q102
sums the ac and dc signals and can drive its 100 Ω
output to ± 2 V. U102, D130, and Q130 provide a
temperature compensated bias voltage for the
overload protection circuits which is adjusted by
P101 to null the dc offset at the input.
DISCRIMINATORS (sheet 2)
Comparators U202, U203, U204, U209
discriminate the AMP 1 and AMP 2 outputs into
ECL levels. U202 is the A discriminator when the
input to counter A is INPUT 1. The threshold is
provided by analog voltage A_DISC and buffered
by 1/4 U208. The output transistor, 1/4 U207,
provides a high frequency, low impedance output.
The comparator is operated in the Schmitt trigger
configuration with about 20 mV of hysteresis.
Since the input signal has been amplified by 5, this
represents about 4 mV of hysteresis at the input.
Control signal A_POL inverts the comparator
output in 1/4 U1206 if the discriminator slope is
set to FALL.
U203 is the B discriminator when the input to
counter B is INPUT 1. If the input to counter B is
INPUT 2, U209 is the B discriminator. Operation
is identical to the A discriminator except that the
outputs of U203 and U209 are multiplexed
through U210. The B_SEL line selects the
appropriate output and B_POL programs the
slope.
U204 is the T discriminator when the input to
counter T is INPUT 2.
The comparators may be inhibited by the
DISC_INH signal which is derived from the
INHIBIT input on the rear panel. When
DISC_INH is asserted, the comparators will be
inactive and their outputs frozen.
U201 is the gate trigger discriminator. It operates
like the input discriminators except that it has
about 75 mV of hysteresis.
A AND B COUNTERS (sheets 3 and 5)
There are 2 gated counting channels capable of
220 MHz operation and essentially infinite count
capacity. Counter A will is described below.
The input to counter A is selected by 2/4 and 3/4
of U301. The signal APULSE_INH disables input