Specifications

SR400 Circuit Description
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SR400 CIRCUIT DESCRIPTION
The SR400 has five printed circuit boards. Almost
all of the components are located on the main
circuit board, including the microprocessor and
interfaces, fast counters and discriminators, gate
generators, and digital to analog conversion
circuits. There is one circuit board in the power
supply enclosure. The other three circuit boards
are much smaller and are mounted to the front
panel. They hold the 2 line by 24 character LCD
display, the key pad, and the status LED
indicators.
MICROPROCESSOR CONTROL
MICROPROCESSOR SYSTEM (sheet 12)
The microprocessor, U1206, is a Z8800 (Super 8)
microcontroller which integrates a fast processor,
UART, counter-timers, interrupt controller, DMA
controller, and RAM into one VLSI component.
This high degree of integration is essential to the
performance of the SR400.
The Super 8 is clocked by the 20 MHz crystal time
base oscillator. The data bus is multiplexed with
the lower 8 bits of the address bus. U1207 latches
the address bits at the start of every memory cycle.
The firmware and calibration bytes are stored in
the 32K x 8 UVEPROM, U1208. U1209 is a 32K
x 8 CMOS static RAM. The large RAM allows
large scans (up to 2000 points) to be internally
buffered. The RAM is battery backed up allowing
instrument settings to be saved. Q1201-3 perform
power-up and power-down reset and RAM
protection.
I/O port strobes are generated by U1201 and
U1211, RD and WR are decoded by U1203.
RS-232 INTERFACE (sheet 12)
The Super 8 has an on-chip UART and baud rate
generator. U1205 level shifts and buffers the
signals to the external connector. The connector is
a data communications equipment (DCE) type.
The baud rate is derived from the processor clock.
Any standard baud rate from 300 to 19.2K baud
may be programmed.
GPIB INTERFACE (sheet 13)
The GPIB (IEEE-488) interface is provided by the
TMS9914A controller, U1311. U1309 and U1310
buffer data I/O to the GPIB connector. U1311 is
programmed to interrupt to the processor
whenever there is bus activity addressed to the
SR400.
INPUT PORTS (sheet 13)
U1301 and U1302 read the prescale bits from
counters A and B. They are latched by CTR_1 to
provide unambiguous data while the counters are
counting. U1303 is the keyboard input buffer. The
upper bits of U1301-3 are used to read various
status signals.
SLOW COUNTERS (sheet 13)
U1304-8 are 5 MHz 8253 VLSI counters. Each
chip has 3 multi-mode 16 bit counters. These
counters count the middle bits in counters A,B,
and T, the gate delay and width oscillators, and the
crystal time base for the dwell time.
OUTPUT PORTS (sheet 14)
U1401-1406 are 8 bit data latches. U1401,
U1402, and U1406 provide control bits for the
discriminators, counters, and gates. U1403 holds
the preset value for the T counter. U1404 and
U1405 drive the front panel LED indicators and
keyboard strobes.
FRONT PANEL (sheets 12,13,14,16)
The front panel is connected to the main board
through 5 cables.
The knob is an optical encoder buffered by U1202.
Each transition of its outputs interrupts the
processor which keeps track of its direction and
speed.
The LCD display connects directly to the
processor data bus. Besides the 8 data lines, there