User guide

36 Altera Corporation
Stratix II Professional Filtering Lab
6. Double-click the Counter Circuit block to view the counter circuit
subsystem, as shown in Figure 27.
Figure 27. Counter Circuit Block
When the clken input signal is high, the counter circuit generates a
signal count_reached that generates a pulse every 4,095 clock
cycles. In “Perform SignalTap II Analysis”, the falling edge of the
signal count_reached is set as a trigger in the SignalTap II
Analysis block. The minimum 4,095 clock cycle delay ensures that
the data is stable on the output of the on-board anti-aliasing filter,
which is connected to the D/A converter, before the SignalTap II
logic analyzer begins to capture data.
f For more information on how the counter circuit is used, see “Perform
SignalTap II Analysis” on page 37.