User guide

Altera Corporation 35

Exercise 4: Analyze & Compare the Results in Hardware

Review Changes Made to the Filtering Lab Design

To review the changes made to the filtering lab design, follow these steps:

1. Run the MATLAB software.

2. In the Current Directory list in the desktop toolbar, browse to the

directory:

<install-path>\StratixII_Pro_DSP_Kit-v1.0.0 \Examples\HW\

Lab\Filtering\Exercise4

3. Click OK.

4. Choose Open (File menu), select filter_design.mdl, and click Open.

5. Review the schematic design (see Figure 22).

The filtering design in Exercise 4 is the same one used in Exercises 1,

2, and 3 (see Figure 4), except:

● The output of the adder is not directly connected to the input of

the filter. The adder output is connected to a D/A converter and

the filter input is connected to an A/D converter. The combined

NCO-generated sinusoids are converted from digital to analog

via the on-board D/A converter. The signal exits the Stratix II

EP2S180 DSP development board via the D/A SMA connector,

loops back into the Stratix II EP2S180 DSP development board

through the A/D SMA connector, and is converted from analog

to digital by the on-board A/D converter before re-entering the

EP2S180.

● The output of the adder is fed to a bitwise XOR function. The XOR

function converts the output from two’s complement format to

unsigned integer format by inverting the most significant bit

(MSB) to add a DC offset of 2

. This conversion is needed

because the D/A converter assumes the input samples are

unsigned integers.

● A register is placed after the bitwise XOR function to reduce the

(clock to output delay) of the transmit circuitry.

● A counter circuit generates a pulse every 4,095 clock cycles after

reset is asserted. This is described in step 6.