User guide

29 Altera Corporation
Stratix II Professional Filtering Lab
Exercise 4:
Analyze &
Compare the
Results in
Hardware
In Exercise 4, you will do the following tasks:
1. “Set Up the Stratix II EP2S180 DSP Development Board for
Hardware Analysis”.
2. “Review Changes Made to the Filtering Lab Design” on page 35.
3. “Configure the EP2S180 FPGA With the Filtering Lab Design” on
page 37.
4. “Perform SignalTap II Analysis” on page 37.
Figure 22 shows the top-level schematic for the filtering lab design you
will use in this exercise. Two numerically controlled oscillators (NCOs)
generate a 1-MHz sinusoidal signal and a 10-MHz sinusoidal signal
respectively. The signals are added together on-chip before they pass
through a digital-to-analog (D/A) converter on the Stratix II Professional
EP2S180 DSP development board. The resulting analog signal is looped
back to an analog-to-digital (A/D) converter on the Stratix II Professional
EP2S180 DSP development board and then passed to an on-chip, low-
pass filter with a cut-off frequency of 3 MHz. The low-pass filter removes
the 10-MHz sinusoidal signal and allows the 1-MHz sinusoidal signal
through to the fir_result output.