User guide

26 Altera Corporation
Stratix II Professional Filtering Lab
Figure 19. Signal Compiler 5.0.1 - page 2 of 2, Hardware Compilation Feature
4. Under Project Settings Options, in the Synthesis tool list, select
Quartus II.
5. Under Project Settings Options, click the Testbench tab and turn
on Generate Stimuli for VHDL Testbench.
6. Under Hardware Compilation, under Single step compilation,
click 1 - Convert MDL to VHDL. The SignalCompiler generates a
simulation script, tb_filter_design.tcl, and a VHDL testbench that
imports the Simulink input stimuli, tb_filter_design.vhd.
7. Click OK.
8. Run the simulation in Simulink to generate the input stimulus files
by choosing Start (Simulation menu).
9. When you are finished generating the input stimulus files, close the
filtering lab design file.