User guide

Appendix A: Programming the Flash Memory Device A–5
Restoring the MAX V CPLD to the Factory Settings
December 2014 Altera Corporation Stratix V GX FPGA Development Kit
User Guide
1 DIP switch SW3.1 set to on includes the MAX V device in the JTAG chain.
2. Launch the Quartus II Programmer.
3. Click Auto Detect.
4. Click Add File and select <install
dir>\kits\stratixVGX_5sgxea7kf40_fpga\factory_recovery\max5.pof.
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX V CPLD.
Configuration is complete when the progress bar reaches 100%.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the Stratix V GX FPGA Development Kit page of the
Altera website.