User guide

December 2014 Altera Corporation Stratix V GX FPGA Development Kit
User Guide
A. Programming the Flash Memory
Device
CFI Flash Memory Map
Table A–1 shows the default memory contents of two interlaced 512-Mbyte CFI flash
devices. Each flash device has a 16-bit data bus and the two combined flash devices
allow for a 32-bit flash memory interface.
For the Board Update Portal to run correctly and update designs in the user memory,
this memory map must not be altered.
c Altera recommends that you do not overwrite the factory hardware and factory
software images unless you are an expert with the Altera tools. If you unintentionally
overwrite the factory hardware or factory software image, refer to “Restoring the
Flash Device to the Factory Settings” on page A–3.
Preparing Design Files for Flash Programming
The following sections use these file types:
■ Nios II Flash Programmer File (.flash)
■ Executable and Linking Format File (.elf)
■ SRAM Object File (.sof)
■ S-Record File (.srec)
You can obtain designs containing prepared .flash files from the Stratix V GX FPGA
Development Kit page of the Altera website. You can also create .flash files from your
own custom design.
Table A–1. Byte Address Flash Memory Map
Block Description Size (KB) Address Range
Board test system scratch 256 0x07FC.0000 - 0x07FF.FFFF
User software 14,336 0x071C.0000 - 0x07FB.FFFF
Factory software 8,192 0x069C.0000 - 0x071B.FFFF
zipfs (html, web content) 8,192 0x061C.0000 - 0x069B.FFFF
User hardware 2 33,280 0x0414.0000 - 0x061B.FFFF
User hardware 1 33,280 0x020C.0000 - 0x0413.FFFF
Factory hardware 33,280 0x0004.0000 - 0x020B.FFFF
PFL option bits 64 0x0003.0000 - 0x0003.FFFF
Board information 64 0x0002.0000 - 0x0002.FFFF
Ethernet option bits 64 0x0001.0000 - 0x0001.FFFF
User design reset vector 64 0x0000.0000 - 0x0000.FFFF