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Chapter 2: Board Components 2–17
Configuration, Status, and Setup Elements
October 2014 Altera Corporation Stratix V GX FPGA Development Board
Reference Manual
Figure 2–4 shows the PFL configuration.
f For more information on the flash memory map storage, refer to the Stratix V GX
FPGA Development Kit User Guide.
FPGA Programming over External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
(U15) using an external USB-Blaster device with the Quartus II Programmer running
on a PC. The external USB-Blaster connects to the board through the JTAG header
(J10).
Figure 2–4. PFL Configuration