User guide

5–30 Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 5–6 shows the parameters that Table 5–3 through Table 5–5 refer to.
rsu_read_latency Output —
The rsu_read_latency output is then set to the read latency (in
phy_clk cycles) using the rsu_codvw_phase resynchronization
clock phase. If calibration is unsuccessful then this signal is
undefined.
rsu_no_dvw_err Output —
If the sequencer sweeps the resynchronization clock across every
phase and does not see any valid data at any phase position, then
calibration fails and this output is set to 1.
rsu_grt_one_dvw_
err
Output —
If the sequencer sweeps the resynchronization clock across every
phase and sees multiple data valid windows, this is indicative of
unexpected read data (random bit errors) or an incorrectly
configured PLL that must be resolved. Calibration has failed and this
output is set to 1.
Notes to Table 5–5:
(1) The debug interface uses the simple Avalon-MM interface protocol.
(2) These ports exist in the Quartus II software, even though the debug interface is for Altera’s use only.
Table 5–5. Other Interface Signals (Part 4 of 4)
Signal Name Type Width Description
Table 5–6. Parameters
Parameter Name Description
DWIDTH_RATIO
The data width ratio from the local interface to the memory interface. DWIDTH_RATIO of
2 means full rate, while
DWIDTH_RATIO of 4 means half rate.
LOCAL_IF_DWIDTH
The width of the local data bus must be quadrupled for half-rate and doubled for
full-rate.
MEM_IF_DWIDTH
The data width at the memory interface. MEM_IF_DWIDTH can have values that are
multiples of
MEM_IF_DQ_PER_DQS .
MEM_IF_DQS_WIDTH The number of DQS pins in the interface.
MEM_IF_ROWADDR_WIDTH The row address width of the memory device.
MEM_IF_BANKADDR_WIDTH The bank address with the memory device.
MEM_IF_CS_WIDTH
The number of chip select pins in the interface. The sequencer only calibrates one chip
select pin.
MEM_IF_DM_WIDTH The number of mem_dm pins on the memory interface.
MEM_IF_DQ_PER_DQS The number of mem_dq[] pins per mem_dqs pin.
MEM_IF_CLK_PAIR_COUNT The number of mem_clk/mem_clk_n pairs in the interface.